LM1973M National Semiconductor, LM1973M Datasheet - Page 3

• Manufacturer Part Number: LM1973M
• Description: Audio Power Amplifier IC
• Manufacturer: National Semiconductor

Specifications of LM1973M

• No. Of Pins: 20
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 20-WSOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Electrical Characteristics
Pin Description
Signal Ground (1, 5, 17): Each input has its own indepen-
dent ground, GND1, GND2, and GND3.
Signal Input (2, 4, 18): There are 3 independent signal in-
puts, IN1, IN2, and IN3.
Signal Output (6, 16, 20): There are 3 independent signal
outputs, OUT1, OUT2, and OUT3.
Voltage Supply (13, 15): Positive voltage supply pins, V
and V
Voltage Supply (7, 19): Negative voltage supply pins, V
and V
tion.
AC Ground (3, 14): These two pins are not physically con-
nected to the die in any way (i.e., No bondwires). These pins
must be AC grounded to prevent signal coupling between
any of the pins nearby. Pin 14 should be connected to pins
13 and 15 for ease of wiring and the best isolation.
Logic Ground (8): Digital signal ground for the interface
lines; CLOCK, LOAD/SHIFT, DATA-IN and DATA-OUT.
Clock (9): The clock input accepts a TTL or CMOS level sig-
nal. The clock input is used to load data into the internal shift
register on the rising edge of the input clock waveform.
Load/Shift (10): The load/shift input accepts a TTL or
CMOS level signal. This is the enable pin of the device, al-
lowing data to be clocked in while this input is low (0V).
Data-In (11): The data-in input accepts a TTL or CMOS level
signal. This pin is used to accept serial data from a micro-
controller that will be latched and decoded to change a chan-
nel’s attenuation level.
DD2
SS2
. To be tied to ground in a single supply configura-
.
(Notes 1, 2) (Continued)
FIGURE 2. Timing Diagram
DD1
SS1
3
Data-Out (12): This pin is used in daisy-chain mode where
more than one µPot is controlled via the same data line. As
the data is clocked into the chain from the µC, the preceding
data in the shift register is shifted out the DATA-OUT pin to
the next µPot in the chain or to ground if it is the last µPot in
the chain. The LOAD/SHIFT line goes high once all of the
new data has been shifted into each of its respective regis-
ters.
Connection Diagram
DS011958-2
DS011958-3
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