LM12L458CIV National Semiconductor, LM12L458CIV Datasheet - Page 7

• Manufacturer Part Number: LM12L458CIV
• Description: A/D Converter (A-D) IC
• Manufacturer: National Semiconductor

Specifications of LM12L458CIV

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Electrical Characteristics
Note 7: V
conversion/comparison accuracy.
Note 8: Accuracy is guaranteed when operating at f
Note 9: With the test condition for V
Note 10: Typical figures are at T
Note 11: Limits are guaranteed to National’s AOQL (Average Output Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error the straight line passes through negative full-scale and zero. (See Figures 7, 8).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between −1 to 0 and 0 to +1 (see Figure 9).
Note 14: The DC common-mode error is measured with both inputs shorted together and driven from 0V to +2.5V. The measured value is referred to the resulting
output value when the inputs are driven with a 1.25V signal.
Note 15: Power Supply Sensitivity is measured after Auto-Zero and/or Auto-Calibration cycle has been completed with V
Note 16: V
Note 17: The LM12L458’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in
a repeatability uncertainty of
Note 18: The Throughput Rate is for a single instruction repeated continuously. Sequencer states 0 (1 clock cycle), 1 (1 clock cycle), 7 (9 clock cycles) and 5 (44
clock cycles) are used (see Figure 15). One additional clock cycle is used to read the conversion result stored in the FIFO, for a total of 56 clock cycles per
conversion. The Throughput Rate is f
Test Circuits and Waveforms
A
+ and V
REFCM
(Reference Voltage Common Mode Range) is defined as (V
D
+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V
±
0.10 LSB.
A
= 25˚C and represent most likely parametric norm.
REF
CLK
= V
(MHz)/N, where N is the number of clock cycles/conversion.
01171116
REF+
FIGURE 1. TRI-STATE Test Circuits and Waveforms
− V
CLK
REF−
01171115
(Continued)
= 6 MHz.
given as +2.5V, the 12-bit LSB is 305 µV and the 8-bit/“Watchdog” LSB is 4.88 mV.
REF+
7
+ V
REF−
)/2.
01171104
A
+ and V
01171118
D
+ at the specified extremes.
01171117
+
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