HSP45102SC-33 Intersil, HSP45102SC-33 Datasheet - Page 3

• Manufacturer Part Number: HSP45102SC-33
• Description: IC's, Digital Signal Processors
• Manufacturer: Intersil

Specifications of HSP45102SC-33

• Frequency: 33MHz
• No. Of Pins: 28
• Peak Reflow Compatible (260 C): No
• Program Memory Type: 12-bit Numerically Controlled Oscillator/Modulator
• Leaded Process Compatible: No
• Mounting Type: Surface Mount

Pin Description
All inputs are TTL level, with the exception of CLK.
Overline designates active low signals.
MSB/LSB
SEL_L/M
ENPHAC
OUT0-11
SFTEN
NAME
LOAD
SCLK
TXFR
GND
P0-1
V
CLK
SD
CC
TYPE
O
I
I
I
I
I
I
I
I
I
I
3
+5V power supply pin.
Ground
Phase modulation inputs (become active after a pipeline delay of four clocks). A phase shift of 0°, 90°,
180°, or 270° can be selected as shown in Table 1.
NCO clock. (CMOS level)
This pin clocks the frequency control shift register.
A high on this input selects the least significant 32 bits of the 64-bit frequency register as the input to
the phase accumulator; a low selects the most significant 32 bits.
The active low input enables the shifting of the frequency register.
This input selects the shift direction of the frequency register. A low on this input shifts in the data LSB
first; a high shifts in the data MSB first.
This pin, when low, enables the clocking of the Phase Accumulator. This input has a pipeline delay of
four clocks.
Data on this pin is shifted into the frequency register by the rising edge of SCLK when SFTEN is low.
This active low input is clocked onto the chip by CLK and becomes active after a pipeline delay of four
clocks. When low, the frequency control word selected by SEL_L/M is transferred from the frequency
register to the phase accumulator’s input register.
This input becomes active after a pipeline delay of five clocks. When low, the feedback in the phase
accumulator is zeroed.
Output data. OUT0 is LSB. Unsigned.
HSP45102
DESCRIPTION
April 25, 2007
FN2810.9