DSPIC30F6014A-20E/PF Microchip Technology, DSPIC30F6014A-20E/PF Datasheet - Page 2
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DSPIC30F6014A-20E/PF
Manufacturer Part Number
DSPIC30F6014A-20E/PF
Description
Digital Signal Processor
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F6011A-30IPT.pdf
(234 pages)
4.DSPIC30F6011A-30IPT.pdf
(8 pages)
5.DSPIC30F6011A-30IPT.pdf
(10 pages)
6.DSPIC30F6011A-30IPT.pdf
(6 pages)
7.DSPIC30F6011A-30IPT.pdf
(8 pages)
8.DSPIC30F6011A-30IPT.pdf
(16 pages)
Specifications of DSPIC30F6014A-20E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TQFP, 80-VQFP
Package
80TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
68
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC164314 - MODULE SKT FOR PM3 80PFAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6014A-20E/PF
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
DSPIC30F6014A-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F6014A-20E/PF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F6011A/6012A/6013A/6014A
8.
9.
10. I
11. I
12. I
The following sections describe the errata and work
around to these errata, where they may apply.
DS80303E-page 2
PLL Lock Status Bit
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
PSV Operations
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register, on address match if the
Least Significant bits of the address are the same
as the 7-bit reserved addresses.
When the I
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02.
When the I
device generates a glitch on the SDA and SCL
pins, causing a false communication start in a
single-master configuration or a bus collision in a
multi-master configuration.
2
2
2
C Module: 10-bit Addressing Mode
C Module: 10-bit Addressing Mode
C Module
2
2
C module is enabled, the dsPIC
C module is configured as a 10-bit
®
DSC
1. Module: CPU –
EXAMPLE 1:
2. Module: Output Compare in PWM Mode
L0:daw.b
L1: ....
The Decimal Adjust instruction, DAW.b, may
improperly clear the Carry bit, C (SR<0>), when
executed.
Work around
Check the state of the Carry bit prior to executing
the DAW.b instruction. If the Carry bit is set, set the
Carry bit again after executing the DAW.b
instruction. Example 1 shows how the application
should process the Carry bit during a BCD addition
operation.
If the desired duty cycle is ‘0’ (OCxRS = 0), the
module will generate a high level glitch of 1 T
Additionally, on the next cycle after the glitch, the
OC pin does not go high, or, in other words, it
misses the next compare for any value written on
OCxRS.
Work around
There are two possible solutions to this problem:
1. Load a value greater than ‘0’ to the OCxRS
2. If the application requires 0% duty cycles, the
.include “p30fxxxx.inc”
.......
mov.b
mov.b
add.b
bra
daw.b
bset.b
bra
register when operating in PWM mode. In this
case, no 0% duty cycle is achievable.
output compare module can be disabled for
0% duty cycles, and re-enabled for non-zero
percent duty cycles.
#0x80, w0
#0x80, w1
w0, w1, w2 ;Perform addition
NC, L0
w2
L1
w2
SR, #C
DAW.b
CHECK CARRY BIT BEFORE
DAW.b
© 2008 Microchip Technology Inc.
;First BCD number
;Second BCD number
;If C set go to L0
;If not,do DAW and
;set the carry bit
;and exit
Instruction
CY
.