DSPIC30F6010AT-20E/PT Microchip Technology, DSPIC30F6010AT-20E/PT Datasheet - Page 11

• Manufacturer Part Number: DSPIC30F6010AT-20E/PT
• Description: IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010AT-20E/PT

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERXLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 35-3:
© 2008 Microchip Technology Inc.
Note 1: If there are no pending transmissions, SPI1TXB is transferred to SPI1SR as soon as the user application writes to
SPIRBF
(SPI1STAT<0>)
SPITBF
SCK1
(CKP = 0
CKE = 0)
SCK1
(CKP = 1
CKE = 0)
SCK1
(CKP = 0
CKE = 1)
SCK1
(CKP = 1
CKE = 1)
SDO1
(CKE = 0)
SDO1
(CKE = 1)
SDI1
(SMP = 0)
Input
Sample
(SMP = 0)
SDI1
(SMP = 1)
Input
Sample
(SMP = 1)
SPI1IF
User application
writes to
SPI1BUF
2: Four SPI1 Clock modes are shown to demonstrate CKP (SPI1CON1<6>) and CKE (SPI1CON1<8>) bit functionality
3: SDI1 and input sample are shown for two different values of the SMP (SPI1CON1<9>) bit for demonstration purposes
4: Operation for 8-bit mode is shown. Except for the number of clock pulses, the 16-bit mode is similar.
SPI1BUF.
only. Only one of the four modes can be chosen for operation.
only. Only one of the two configurations of the SMP bit can be chosen during operation.
(2)
(2)
(2)
(2)
(3)
(3)
(3)
(3)
SPI1 Master Mode Timing
Section 35. Serial Peripheral Interface (SPI) (Part II)
bit 7
bit 7
bit 7
SPI1TXB to SPI1SR
bit 7
User application
reads SPI1BUF
bit 6
bit 6
(1)
bit 5
bit 5
bit 4
bit 4
bit 3
1 instruction cycle latency to set
SPI1IF flag bit
bit 3
User application writes new
data during transmission
bit 2
bit 2
SPI1SR moved
into SPI1RXB
bit 1
bit 1
bit 0
bit 0
bit 0
bit 0
DS70272B-page 35-11
4 Clock
modes
(clock
output at
the SCK1
pin in
Master
mode)
Two modes
available
for SMP
control
bit
(4)
35