DSPIC30F3013T-30I/ML Microchip Technology, DSPIC30F3013T-30I/ML Datasheet - Page 103
DSPIC30F3013T-30I/ML
Manufacturer Part Number
DSPIC30F3013T-30I/ML
Description
IC,DSP,16-BIT,CMOS,LLCC,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(6 pages)
4.DSPIC30F2011-20IP.pdf
(26 pages)
5.DSPIC30F3012-20ISO.pdf
(14 pages)
6.DSPIC30F3012-20ISO.pdf
(20 pages)
Specifications of DSPIC30F3013T-30I/ML
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20ISO PDF datasheet #2
- DSPIC30F2011-20ISO PDF datasheet #3
- DSPIC30F2011-20IP PDF datasheet #4
- DSPIC30F3012-20ISO PDF datasheet #5
- DSPIC30F3012-20ISO PDF datasheet #6
- Current page: 103 of 210
- Download datasheet (3Mb)
TABLE 14-2:
I2CRCV
I2CTRN
I2CBRG
I2CCON
I2CSTAT
I2CADD
Legend:
SFR Name Addr.
Note:
0200
0202
0204
0206
0208
020A
— = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
ACKSTAT TRSTAT
I
2
I2CEN
Bit 15
C REGISTER MAP
—
—
—
—
Bit 14
—
—
—
—
—
I2CSIDL SCLREL IPMIEN
Bit 13
—
—
—
—
—
Bit 12
—
—
—
—
—
Bit 11
—
—
—
—
—
Bit 10
A10M
BCL
—
—
—
—
GCSTAT ADD10
DISSLW
Bit 9
—
—
—
SMEN
Bit 8
—
—
IWCOL
GCEN
Bit 7
STREN
I2COV
Bit 6
Address Register
ACKDT
Bit 5
D_A
Baud Rate Generator
Transmit Register
Receive Register
ACKEN
Bit 4
P
RCEN
Bit 3
S
Bit 2
R_W
PEN
RSEN
Bit 1
RBF
Bit 0
SEN
TBF
0000 0000 0000 0000
0000 0000 1111 1111
0000 0000 0000 0000
0001 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Reset State
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