DSPIC30F2020T-30I/SO Microchip Technology, DSPIC30F2020T-30I/SO Datasheet - Page 28
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DSPIC30F2020T-30I/SO
Manufacturer Part Number
DSPIC30F2020T-30I/SO
Description
12KB, Flash, 512bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 SOIC .300in
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F1010-30ISO.pdf
(26 pages)
4.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F2020T-30I/SO
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F2020T-30I/SOTR
11.3
Figure 11-4
ICSP Program/Verify mode:
1.
2.
3.
The programming voltage applied to MCLR is V
which is essentially V
SMPS devices. There is no minimum time requirement
for holding at V
least P16 must elapse before presenting the key
sequence on PGD.
FIGURE 11-4:
DS70284C-page 28
MCLR is briefly driven high then low.
A 32-bit key sequence is clocked into PGD.
MCLR is then driven high within a specified
period of time and held.
MCLR
V
PGD
PGC
DD
Entering ICSP Mode
shows the three required steps to enter the
IH
. After V
P6
ENTERING ICSP™ MODE
DD
IH
is removed, an interval of at
in the case of dsPIC30F
P12
P16
V
b31
IH
0
b30
1
Program/Verify Entry Code = 0x4D434851
b29
IH
0
,
b28
P2B
0
P2A
b27
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0001’
(more
hexadecimal). The device will enter Program/Verify
mode only if the sequence is valid. The Most Significant
bit of the most significant nibble must be shifted in first.
Once the key sequence is complete, V
applied to MCLR and held at that level for as long as
Program/Verify mode has to be maintained. An interval
of at least time P17 and P7 must elapse before
presenting data on PGD. Signals appearing on PGD
before P7 has elapsed will not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
ICSP mode, all unused I/Os are placed in the
high-impedance state.
1
...
easily
b3
0
b2
remembered
0
b1
0
V
© 2010 Microchip Technology Inc.
IH
b0
1
as
P17
0x4D434851
P7
IH
must be
in