DSPIC30F1010T-30I/MM Microchip Technology, DSPIC30F1010T-30I/MM Datasheet - Page 122
![6KB, Flash, 256bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 QFN-S 6x6mm T](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC30F1010T-30I/MM
Manufacturer Part Number
DSPIC30F1010T-30I/MM
Description
6KB, Flash, 256bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 QFN-S 6x6mm T
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F1010T-30I/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
6KB (2K x 24)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Data Bus Width
16 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
21
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCK
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
DSPIC30F1010T-30I/MMTR
- AC164335 PDF datasheet
- DM300023 PDF datasheet #2
- DM300023 PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20IP PDF datasheet #5
- DSPIC30F1010-30ISO PDF datasheet #6
- DSPIC30F1010-30ISO PDF datasheet #7
- Current page: 122 of 286
- Download datasheet (5Mb)
dsPIC30F1010/202X
REGISTER 12-14: LEBCONx: LEADING EDGE BLANKING CONTROL REGISTER
DS70178C-page 120
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-3
bit 2-0
R/W-0
R/W-0
PHR
PHR: PWMH Rising Edge Trigger Enable bit
1 = Rising edge of PWMH will trigger LEB counter
0 = LEB ignores rising edge of PWMH
PHL: PWMH Falling Edge Trigger Enable bit
1 = Falling edge of PWMH will trigger LEB counter
0 = LEB ignores falling edge of PWMH
PLR: PWML Rising Edge Trigger Enable bit
1 = Rising edge of PWML will trigger LEB counter
0 = LEB ignores rising edge of PWML
PLF: PWML Falling Edge Trigger Enable bit
1 = Falling edge of PWML will trigger LEB counter
0 = LEB ignores falling edge of PWML
FLTLEBEN: Fault Input Leading Edge Blanking Enable bit
1 = Leading Edge Blanking is applied to selected Fault Input
0 = Leading Edge Blanking is not applied to selected Fault Input
CLLEBEN: Current-Limit Leading Edge Blanking Enable bit
1 = Leading Edge Blanking is applied to selected Current-Limit Input
0 = Leading Edge Blanking is not applied to selected Current-Limit Input
LEB: Leading Edge Blanking for Current-Limit and Fault Inputs bits
Value is 8 nsec increments
Unimplemented: Read as ‘0’
R/W-0
R/W-0
PHF
W = Writable bit
‘1’ = Bit is set
LEB<7:3>
R/W-0
R/W-0
PLR
R/W-0
R/W-0
PLF
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
FLTLEBEN
R/W-0
R/W-0
CLLEBEN
R/W-0
U-0
—
© 2006 Microchip Technology Inc.
x = Bit is unknown
R/W-0
U-0
—
LEB<9:8>
R/W-0
U-0
—
bit 8
bit 0
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