DS90CF366MTD National Semiconductor, DS90CF366MTD Datasheet - Page 3

• Manufacturer Part Number: DS90CF366MTD
• Description: IC,Serial-to-Parallel Converter,CMOS,TSSOP,48PIN
• Manufacturer: National Semiconductor

Specifications of DS90CF366MTD

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CLHT
CHLT
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
RECEIVER SUPPLY CURRENT
ICCRZ
Symbol
Symbol
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable), and clock jitter (less than 150 ps).
Receiver Supply Current
Power Down
CMOS/TTL Low-to-High Transition Time (Figure 4 )
CMOS/TTL High-to-Low Transition Time (Figure 4 )
Receiver Input Strobe Position for Bit 0 (Figure 11,
Figure 12 )
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 4) (Figure 13 )
RxCLK OUT Period (Figure 5)
RxCLK OUT High Time (Figure 5 )
RxCLK OUT Low Time (Figure 5)
RxOUT Setup to RxCLK OUT (Figure 5 )
RxOUT Hold to RxCLK OUT (Figure 5 )
RxCLK IN to RxCLK OUT Delay
Receiver Phase Lock Loop Set (Figure 7 )
Receiver Power Down Delay (Figure 10 )
OD
and ∆V
Parameter
OD
).
CC
= 3.3V and T
Parameter
@
A
(Continued)
= +25C.
25˚C, V
(Figures 2, 3, 4 )
Power Down = Low
Receiver Outputs Stay Low during
Power Down Mode
CC
= 3.3V (Figure 6 )
3
Conditions
f = 85 MHz
f = 85 MHz
f = 85 MHz
f = 65 MHz
f = 85 MHz
10.57
11.76
0.49
2.17
3.85
5.53
7.21
8.89
Min
290
4.5
4.0
2.0
3.5
5.5
Min
10.92
0.84
2.52
4.20
5.88
7.56
9.24
Typ
2.0
1.8
7.0
T
5
5
Typ
140
43
43
11.27
Max
1.19
2.87
4.55
6.23
7.91
9.59
3.5
3.5
6.5
9.5
50
10
Max
400
7
1
60
70
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Units
Units
mA
mA
µA
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
µs