CS5507-AP Cirrus Logic Inc, CS5507-AP Datasheet
CS5507-AP
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CS5507-AP Summary of contents
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... Description The CS5505/6/7/8 are a family of low power CMOS A/D converters which are ideal for measuring low-frequency signals representing physical, chemical, and biological processes. The CS5507/8 have single-channel differential analog and reference inputs while the CS5505/6 have four pseudo-differential analog input CS5505/7 have a 16-bit output word. The CS5506/8 have a 20-bit output word ...
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... Unipolar Mode % FS ppm FS 0.0004 4 0.0008 8 0.0015 15 0.0030 30 0.0061 61 VREF = 2.5V CS5505/7; 16-Bit Unit Conversion Factors CS5505/6/7 10%; VA source CS5507-S Max Min Typ Max -55 to +125 0.003 - 0.0015 0.003 - 0 0.16 Bipolar Mode LSB’ ...
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ANALOG CHARACTERISTICS 3.3V 5%; VREF+ = 2.5V (external); VREF- = 0V; f 10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2) Parameter* Specified Temperature Range Accuracy Linearity Error Differential Nonlinearity (No ...
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... Min Typ Max - +2.5 (Note 5) 2 105 120 - - 120 - 15 (Note (VA+)- 340 450 Total I - 300 Analog Digital (Note 7) - 3.2 4 CS5505/6/7/8 10%; VA- = -5V 10%; VD source CS5507/8-S Min Typ Max -55 to +125 0 to +2.5 2 105 - - 120 - - - - 120 - - - (VA+)- 340 450 - - 300 - - ...
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DIGITAL CHARACTERISTICS DGND = 0.) All measurements below are performed under static conditions. (Note 2) Parameter High-Level Input Voltage: All Pins Except XIN and M/SLP Low-Level Input Voltage: All Pins Except XIN and M/SLP M/SLP SLEEP Active Threshold High-Level ...
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SWITCHING CHARACTERISTICS VA- = -5V 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C Parameter Master Clock Frequency: Internal Oscillator: External Clock: Master Clock Duty Cycle Rise Times: Any Digital Input Any Digital Output Fall Times: ...
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SWITCHING CHARACTERISTICS VD+ = 3.3V 5%; VA- = -5V 10%; Input Levels: Logic 0 = 0V, Logic pF.) (Note 2) Parameter Master Clock Frequency: Internal Oscillator: External Clock: Master Clock Duty Cycle Rise ...
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XIN XIN/2 CAL CONV STATE Standby XIN XIN/2 A0, A1 CONV DRDY BP/UP STATE Standby 8 t ccw t t scl cal Calibration Figure 1. Calibration Timing (Not to Scale hca sac t cpw t scn Conversion Figure ...
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SWITCHING CHARACTERISTICS VA- = -5V 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C Parameter SSC Mode (M/SLP = VD+) Access Time: CS Low to SDATA out (DRDY = low) DRDY falling to MSB (CS = ...
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SWITCHING CHARACTERISTICS 5%; VA- = -5V 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C Parameter SSC Mode (M/SLP = VD+) Access Time: CS Low to SDATA out (DRDY = low) DRDY falling to MSB (CS ...
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XIN XIN/2 CONV CS STATE Standby DRDY SCLK(o) Hi-Z SDATA(o) Hi-Z STATE (CONV held high) Figure 3. Timing Relationships; SSC Mode (Not to Scale) DRDY CS t csd2 SDATA(o) Hi-Z SCLK(i) DRDY CS t csd2 SDATA(o) Hi-Z SCLK(i) Figure 4. ...
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RECOMMENDED OPERATING CONDITIONS Parameter DC Power Supplies: Positive Digital (VA+)-(VA-) Positive Analog Negative Analog Analog Reference Voltage (Note 20) (VREF+)-(VREF-) Analog Input Voltage: (Note 21) Unipolar Bipolar Notes: 19. All voltages with respect to ground. 20. The CS5505/6/7/8 can be ...
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GENERAL DESCRIPTION The CS5505/6/7/8 are very low power mono- lith A/D co nverters designed specifically for measurement of dc signals. The CS5505/7 are 16-bit converters (a four channel and a single channel version). The CS5506/8 are 20-bit ...
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The calibration state is entered whenever the CAL and CONV pins are high at the same time. The state of the CAL and CONV pins at ...
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AIN1. The BP/UP pin is not a latched input. The BP/UP pin controls how the output word from the digital filter is processed. In bipolar mode the output word computed by the digital filter is offset by 8000H in the ...
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... While the voltage reference can be as great as 3.6 volts, its common mode voltage can be any value as long as the reference inputs VREF+ and VREF- stay within the supply volt- CS5505 and CS5507 (16 Bit) Unipolar Input Output Voltage Codes > ...
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Understanding Converter Calibration Calibration can be performed at any time. A calibration sequence will minimize offset errors and set the gain slope scale factor. The delta- sigma modulator in the converter is a differential modulator. To calibrate out offset error, ...
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Analog Input Impedance Considerations The analog input of the CS5505/6/7/8 can be modeled as illustrated in Figure 8 (the model ig- nores the multiplexer switch resistance). Capacitors (15 pF each) are used to dynamically sample each of the inputs (AIN+ ...
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Digital Filter Characteristics The digital filter in the CS5505/6/7/8 is the com- bination of a comb filter and a low pass filter. The comb filter has zeros in its transfer function which are optimally placed to reject line interfer- ence ...
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If the CS5505/6/7/8 is operated at a clock rate other than 32.768 kHz, the filter characteristics, including the comb filter zeros, will scale with the operating clock frequency. Therefore, opti- mum rejection of line frequency interference will occur with the ...
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Over the military temperature range (- 55 to +125 C) the on-chip gate oscillator is designed to work only with a 32.768 kHz crys- tal. The chip will ...
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Synchronous External-Clocking Mode The serial port operates in the SEC mode when the M/SLP pin is connected to the DGND pin. SDATA is the output pin for the serial data. When CS goes low after new data becomes available (DRDY ...
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No analog ground pin is re- quired because the inputs for measurement and for the voltage reference are differential and re- quire no ground. In the digital section of the chip the supply current flows into the ...
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Figure 14 illustrates the System Connection Dia- gram for the CS5505/6 using a single +5V supply. Note that all supply pins are bypassed with 0.1 F capacitors and that the VD+ digital supply is derived from the VA+ supply. Figure ...
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Analog Supply Calibration Control Bipolar/ Unipolar Input Select Analog* Signal Sources Signal Ground *Unused analog inputs should be tied to AIN- + Voltage (1) Reference - Note: (1) To use the internal 2.5 volt reference see Figure 6. (2) ...
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... SCLK 4 21 XIN VD XOUT DGND 6 19 M/SLP VA BP/UP VA AIN1+ VREFOUT VOLTAGE REFERENCE OUTPUT 9 16 AIN2+ VREF AIN- VREF AIN3+ AIN4 CS5507 DRDY 2 19 CONV SDATA 3 18 CAL SCLK 4 17 XIN VD XOUT DGND 6 15 M/SLP VA BP/UP VA AIN+ VREFOUT VOLTAGE REFERENCE OUTPUT 9 12 ...
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PIN DESCRIPTIONS Pin numbers for four channel devices are in parentheses. Clock Generator XIN; XOUT - Crystal In; Crystal Out, Pins 4 (5) and 5 (6). A gate inside the chip is connected to these pins and can be used ...
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Control Input Pins CAL - Calibrate, Pin 3 (4). When taken high the same time that the CONV pin is taken high the converter will perform a self-calibration which includes calibration of the offset and gain scale factors in the ...
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VD+ - Positive Digital Power, Pin 17 (20). Positive digital supply voltage. Nominally +5 volts or 3.3 volts. DGND - Digital Ground, Pin 16 (19). Digital Ground. Other Connection, Pin 9. Pin should be left floating. SPECIFICATION ...
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... Ordering Guide Model # of Number Channels CS5505-AP 4 CS5505-AS 4 CS5506-BP 4 CS5506-BS 4 CS5507-AP 1 CS5507-AS 1 CS5507-SD 1 CS5508-BP 1 CS5508-BS 1 CS5508- Resolution Linearity Temperature Error Range ( C) 16-Bits 0.0030% -40 to +85 16-Bits 0.0030% -40 to +85 20-Bits 0.0015% -40 to +85 20-Bits 0.0015% -40 to +85 16-Bits 0.0030% -40 to +85 16-Bits 0.0030% -40 to +85 16-Bits 0.0030% -55 to +125 20-Bits 0 ...
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APPENDIX The following companies provide 32.768 kHz crystals in many package varieties and temperature ranges. Fox Electronics 5570 Enterprise Parkway Fort Meyers, FL 33905 (813) 693-0099 Micro Crystal Division / SMH 702 West Algonquin Road Arlington Heights, IL 60005 (708) ...
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Notes • ...
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Evaluation Board for CS5505/6/7/8 Series of ADC’s Features l Operation with on-board 32.768 kHz crystal or off-board clock source l Jumper selectable: - SSC mode; SEC mode; Sleep l DIP Switch Selectable: - BP/UP mode; A0, & A1 channel selection ...
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Introduction The CDB5505/6/7/8 evaluation board provides a quick means of testing the CS5505/6/7/8 series A/D converters. The CS5505/6/7/8 converters require a minimal amount of external circuitry. The evaluation board comes configured with the A/D converter chip operating from a 32.768 ...
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... F VREFOUT TP10 R27 CONV VREF+ C19 R26 TP9 10nF VREF- C20 10nF TP8 TP7 CS5505 24 A1 CS5506 3A CS5507 TP11 23 OR DRDY 3B CS5508 TP12 TP3 22 SDATA 13 AIN4+ TP13 TP4 21 SCLK 12 AIN3+ TP5 10 AIN2+ TP14 11 TP6 8 BP/UP 9 AIN1+ TP15 C15 7 11 M/SLP ...
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... XIN 5/4 17/20 XOUT 6/5 16/19 M/SLP 7/6 15/18 BU/UP 8/7 14/17 AIN1+ 9/8 13/16 AIN2+/NC 10/9 12/15 AIN- 11/10 11/14 AIN3 Figure 2. CS5505/6 and CS5507/8 Pin Layouts CS5505/6/7/8 A1 DRDY SDATA SCLK VD+ DGND VA- VA+ VREFOUT VREF- VREF+ AIN4+ DS59DB2 ...
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Figure 3. Top Ground Plane Layer (NOT TO SCALE) DS59DB2 CS5505/6/7/8 37 ...
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Figure 4. Bottom Trace Layer (NOT TO SCALE) CS5505/6/7/8 DS59DB2 ...
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DS59DB2 Figure 5. Silk Screen Layer (NOT TO SCALE) CS5505/6/7/8 39 ...
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