CS5351-KS Cirrus Logic Inc, CS5351-KS Datasheet - Page 10

• Manufacturer Part Number: CS5351-KS
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5351-KS

• Input Channels Per Adc: 2
• Mounting Type: Surface Mount
• No. Of Channels: 2
• Supply Voltage Min: 4.75V
• Operating Temperature Max: 70°C
• Peak Reflow Compatible (260 C): No
• Sample Rate: 192kSPS
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

as specified in the Switching Characteristics - Serial Audio Port section. This ensures sufficient time to
detect an overrange condition regardless of the speed mode. After the timeout, the OVFL_L and OVFL_R
data will return to a logical high if there has not been any other overrange condition detected. Please note
that an overrange condition on either channel will restart the timeout period for both channels.
In left-justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I
the OVFL pin is updated two SCLK periods after an LRCK transition. Refer to Figures 23 and 24. In both
cases the OVFL data can be easily demultiplexed by using the LRCK to latch the data. In left-justified
format, the rising edge of LRCK would latch the right channel overflow status, and the falling edge of
LRCK would latch the left channel overflow status. In I
the right channel overflow status and the rising edge of LRCK would latch the left channel overflow status.
3.7
As with any high resolution converter, the CS5351 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figure 1 shows the recommended power
arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be
run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no
additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as
possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The
FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electri-
cal path from FILT+ and REFGND. The CDB5351 evaluation board demonstrates the optimum layout and
power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS
inputs.
3.8
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5351’s in the sys-
tem. If only one master clock source is needed, one solution is to place one CS5351 in Master mode, and
slave all of the other CS5351’s to the one master. If multiple master clock sources are needed, a possible
solution would be to supply all clocks from the same external source and time the CS5351 reset with the
inactive edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.
10
3.6.1
Grounding and Power Supply Decoupling
Synchronization of Multiple Devices
OVFL Output Timing
2
S format, the falling edge of LRCK would latch
CS5351
2
DS565PP2
S format,