CS44800-CQZ Cirrus Logic Inc, CS44800-CQZ Datasheet - Page 24
![IC,Audio Power Amplifier Controller,CMOS,QFP,64PIN](/photos/7/4/70403/mfg_cs44800_series_sml.jpg)
CS44800-CQZ
Manufacturer Part Number
CS44800-CQZ
Description
IC,Audio Power Amplifier Controller,CMOS,QFP,64PIN
Manufacturer
Cirrus Logic Inc
Type
Digital Amplifier Controllerr
Datasheet
1.CS44800-CQZR.pdf
(80 pages)
Specifications of CS44800-CQZ
Applications
Automotive Systems
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1532 - BOARD EVAL FOR CS44800 PWM CTRL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1070
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS44800-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
135
Company:
Part Number:
CS44800-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
24
Additional Features
4.3
DAI_MCLK
DAI_LRCK
DAI_SCLK
DAI_SDINx
SYS_CLK
XTO
XTI
•
•
•
•
•
•
•
•
•
Clock Generation
The sources for internal clock generation for the PWM processing are as follows:
•
•
Digital volume control with soft ramp.
Individual channel volume gain, attenuation and mute capability; +24 to -127 dB in 0.25 dB steps.
Master volume attenuation; +24 to -127 dB in 0.25 dB steps.
Peak Detect and Volume Limiter with programmable attack and release rates.
Signal-clipping interrupt indicator.
Contains a two-stage digital output filter for speaker impedance compensation.
Provides 7 programmable GPIO pins with interrupt generation for easily interfacing to a variety of com-
monly available power state parts. Interrupts can be masked.
Selectable over-sample rate for increased audio bandwidth.
Power supply clock output, PS_SYNC, with programmable divider
FsIn Domain:
FsOut Domain:
–
–
–
DAI_MCLK, minimum 128Fs
XTI/XTO (Fundamental or 3
Clock signal on XTI (VDX is used to set logic voltage level)
Digital Audio
Ratio Detect
Input Port
1, 1.5, 2,
3, 4, 6, 8
XTAL /
CLKIN
1,2,4,8
Emphasis
De-
Figure 13. CS44800 Data Flow Diagram (Single Channel Shown)
FsIn FsOut
128Fs
SRC
SRC_MCLK (128Fs)
Compensation
2-pole Load
Filter
2.25
Clock Control
Channel
Volume
rd
overtone crystal), or
1,1.5,
2,4
Volume
Master
(AM_FREQ_HOP)
Σ
AM Freq. Hop
PWM_MCLK
MOD_MCLK
Over Sample
(OSRATE)
mute
LIMITER
DETECT
PEAK
Over Sample
x2
(OSRATE)
Modulator
Multibit
Σ∆
PWM Engine
Feedback
PSR
Delay
Delay
CS44800
PWM_OUT+
PWM_OUT-
DS632F1