CDB4364 Cirrus Logic Inc, CDB4364 Datasheet - Page 28

• Manufacturer Part Number: CDB4364
• Description: Eval Bd 6Chn DAC W/DSD Spt&Lw-Ltnc DF
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4364

• Number Of Dac's: 6
• Number Of Bits: 24
• Outputs And Type: 6, Single Ended
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS4364
• Description/function: Audio D/A
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS4364
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant

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4.12
4.12.1 Hardware Mode
4.12.2 Software Mode
Recommended Power-Up Sequence
1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
2. Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
2. Bring RST high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in
3. In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the
clocks are locked to the appropriate frequencies, as discussed in
registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2.
If RST can not be held low long enough the SDINx pins should remain static low until all other clocks
are stable, and if possible the RST should be toggled low again once the system is stable.
Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024
LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
appropriate frequencies, as discussed in
settings, FILT+ will remain low, and VQ will be connected to VA/2.
Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-
Speed Mode).
completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-
Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be
loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1, then set the
format and mode control bits to the desired settings.
If more than the stated number of LRCK cycles passes before CPEN bit is written then the chip will
enter Hardware Mode and begin to operate with the M0-M4 as the mode settings. CPEN bit may be
written at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit
can not be set in time then the SDINx pins should remain static low (this way no audio data can be
Figure 21. Recommended Mute Circuitry
Section
4.1. In this state, the registers are reset to the default
Section
4.1. In this state, the
CS4364
DS619F1