SST25VF080B-50-4I-QAF SILICON STORAGE TECHNOLOGY, SST25VF080B-50-4I-QAF Datasheet - Page 18

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SST25VF080B-50-4I-QAF

Manufacturer Part Number
SST25VF080B-50-4I-QAF
Description
8M FLASH MEMORY, SPI EEPROM, WSON-8
Manufacturer
SILICON STORAGE TECHNOLOGY
Datasheet

Specifications of SST25VF080B-50-4I-QAF

Memory Size
8Mbit
Clock Frequency
50MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
WSON
No. Of Pins
8
Svhc
No SVHC (18-Jun-2010)
Package / Case
WSON
Device
RoHS Compliant
Memory Type
Flash
Memory Configuration
1M X 8
Interface Type
Serial, SPI
Rohs Compliant
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SST25VF080B-50-4I-QAF
Manufacturer:
SST
Quantity:
20 000
Data Sheet
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to
the BP3, BP2, BP1, BP0, and BPL bits of the status regis-
ter. CE# must be driven low before the command
sequence of the WRSR instruction is entered and driven
high before the WRSR instruction is executed. See Figure
18 for EWSR or WREN and WRSR instruction sequences.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to “1”. When
the WP# is low, the BPL bit can only be set from “0” to “1” to
lock-down the status register, but cannot be reset from “1”
©2006 Silicon Storage Technology, Inc.
FIGURE 18: E
SCK
CE#
SO
SI
W
MODE 3
MODE 0
NABLE
RITE
-E
-W
NABLE
0 1 2 3 4 5 6 7
MSB
RITE
50 or 06
-S
(WREN)
TATUS
-R
AND
EGISTER
W
RITE
(EWSR)
-S
HIGH IMPEDANCE
MODE 3
MODE 0
TATUS
18
MSB
OR
to “0”. When WP# is high, the lock-down function of the
BPL bit is disabled and the BPL, BP0, and BP1 and BP2
bits in the status register can all be changed. As long as
BPL bit is set to 0 or WP# pin is driven high (V
low-to-high transition of the CE# pin at the end of the
WRSR instruction, the bits in the status register can all be
altered by the WRSR instruction. In this case, a single
WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0, BP1, and
BP2 bits at the same time. See Table 2 for a summary
description of WP# and BPL functions.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-R
EGISTER
01
(WRSR) S
MSB
7 6 5 4 3 2 1 0
REGISTER IN
EQUENCE
STATUS
8 Mbit SPI Serial Flash
SST25VF080B
1296 EWSR.0
S71296-01-000
IH
) prior to the
1/06

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