LFXP3C-5TN100C LATTICE SEMICONDUCTOR, LFXP3C-5TN100C Datasheet - Page 11

• Manufacturer Part Number: LFXP3C-5TN100C
• Description: FPGA, 1.8V FLASH, INSTANT ON, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeXPr

Specifications of LFXP3C-5TN100C

• No. Of Logic Blocks: 384
• No. Of Macrocells: 1500
• Family Type: LatticeXP
• No. Of Speed Grades: 5
• No. Of I/o's: 62
• Clock Management: PLL
• Core Supply Voltage Range: 1.71V To 3.465V
• I/o: RoHS Compliant

Lattice Semiconductor
Figure 2-6. Secondary Clock Sources
Clock Routing
The clock routing structure in LatticeXP devices consists of four Primary Clock lines and a Secondary Clock net-
work per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-7 shows this
clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2-
8. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in Figure 2-
9.
Figure 2-7. Per Quadrant Primary Clock Selection
Clock Input
From Routing
From Routing
From Routing
From Routing
1. Smaller devices have fewer PLL related lines.
2. Dynamic clock select.
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing
Routing
Routing
From
From
Routing
Routing
20 Secondary Clock Sources
To Quadrant Clock Selection
From
From
Clock
Clock
Input
Input
DCS
2-8
2
Routing
Routing
From
From
Routing
Routing
From
From
LatticeXP Family Data Sheet
DCS
1
2
From Routing
From Routing
From Routing
From Routing
Clock Input
Architecture