IS42S16160D-7TLI INTEGRATED SILICON SOLUTION (ISSI), IS42S16160D-7TLI Datasheet - Page 13

• Manufacturer Part Number: IS42S16160D-7TLI
• Description: SDRAM, IND, 16M X 16, 3V, 54TSOP2
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS42S16160D-7TLI

• Access Time: 5.4ns
• Page Size: 256Mbit
• Memory Case Style: TSOP-2
• No. Of Pins: 54
• Operating Temperature Range: -40°C To +85°C
• Memory Type: DRAM - Synchronous
• Memory Configuration: 4 BLK (4M X 16)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S83200D, IS42S16160D
Notes:
1. H : High level, L : low level, X : High or low level (Don’t care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if t
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
12/12/07
CKE RELATED COMMAND TRUTH TABLE
Current State
Self-Refresh (S.R.)
Self-Refresh Recovery Idle After t
Power-Down (P.D.)
All Banks Idle
Any state
other than
listed above
time must be satisfied before any command other than EXIT.
xsr
is not satisfied.
Operation
INVALID, CLK (n - 1) would exit S.R.
Self-Refresh Recovery
Self-Refresh Recovery
Illegal
Illegal
Maintain S.R.
Idle After t
Illegal
Illegal
Begin clock suspend next cycle
Begin clock suspend next cycle
Illegal
Illegal
Exit clock suspend next cycle
Maintain clock suspend
INVALID, CLK (n - 1) would exit P.D.
EXIT P.D. --> Idle
Maintain power down mode
Refer to operations in Operative Command TableH
Refer to operations in Operative Command TableH
Refer to operations in Operative Command TableH
Auto-Refresh
Refer to operations in Operative Command TableH
Refer to operations in Operative Command TableH
Refer to operations in Operative Command TableH
Refer to operations in Operative Command TableH
Self-Refresh
Refer to operations in Operative Command TableH
Power-Down
Refer to operations in Operative Command TableH
Begin clock suspend next cycle
Exit clock suspend next cycle
Maintain clock suspend
rc
rc
(3)
(3)
(2)
(2)
(2)
(2)
(5)
(5)
(4)
(1)
n-1
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
CKE
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
n
X
L
L
L
L
L
L
X
L
L
L
L
L
L
X
L
L
CS
X
H
X
H
H
X
X
X
X
X
H
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
X
X
H
H
X
X
H
H
X
H
H
X
X
X
X
X
X
H
X
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
CAS
X
X
H
X
X
X
H
X
X
H
X
X
X
X
X
X
X
X
H
X
X
H
X
X
X
X
X
L
L
L
L
L
L
L
WE
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
Op - Code
Op - Code
Address
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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