ADC78H89CIMT National Semiconductor, ADC78H89CIMT Datasheet - Page 13

• Manufacturer Part Number: ADC78H89CIMT
• Description: IC, 12BIT ADC 500KSPS, POWERWISE
• Manufacturer: National Semiconductor

Specifications of ADC78H89CIMT

• Resolution (bits): 12bit
• Input Channel Type: Single Ended
• Data Interface: Serial, SPI
• Supply Voltage Range - Analogue: 2.7V To 5.25V
• Supply Voltage Range - Digital: -0.3V To 5.25V, 2.7V To 5.25V
• Sampling Rate: 500kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Applications Information
2.0 ADC78H89 OPERATION
The ADC78H89 is a successive-approximation analog-to-
digital converter designed around a charge-redistribution
digital-to-analog converter. Simplified schematics of the
ADC78H89 in both track and hold modes are shown in
Figure 2 and Figure 3, respectively. In Figure 2, the
ADD2
Bit 7 (MSB)
DONTC
0
0
0
0
1
1
1
1
Bit #:
7, 6, 2, 1, 0
5
4
3
TABLE 2. Input Channel Selection
ADD1
0
0
1
1
0
0
1
1
DONTC
Symbol:
DONTC
ADD2
ADD1
ADD0
Bit 6
ADD0
0
1
0
1
0
1
0
1
ADD2
Input Channel
Bit 5
Description
Don’t care. The value of this bit does not affect the device.
These three bits determine which input channel will be sampled and
converted on the next falling edge of CS. The mapping between codes and
channels is shown in Table 2.
AIN1 (Default)
FIGURE 2. ADC78H89 in Track Mode
(Continued)
FIGURE 3. ADC78H89 in Hold Mode
Control Register Bit Descriptions
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
GND
TABLE 1. Control Register Bits
ADD1
Bit 4
13
ADC78H89 is in track mode: switch SW1 connects the sam-
pling capacitor to one of seven analog input channels
through the multiplexer, and SW2 balances the comparator
inputs. The ADC78H89 is in this state for the first three SCLK
cycles after CS is brought low.
The user does not need to worry about any kind of power-up
delays or dummy conversions with the ADC78H89. The part
is able to acquire input to full resolution in the first conversion
immediately following power-up. The first conversion after
power up will be that of the first channel.
Figure 3 shows the ADC78H89 in hold mode: switch SW1
connects the sampling capacitor to ground, maintaining the
sampled voltage, and switch SW2 unbalances the compara-
tor. The control logic then instructs the charge-redistribution
DAC to add or subtract fixed amounts of charge from the
sampling capacitor until the comparator is balanced. When
the comparator is balanced, the digital word supplied to the
DAC is the digital representation of the analog input voltage.
The ADC78H89 is in this state for the last thirteen SCLK
cycles after CS is brought low.
ADD0
Bit 3
DONTC
Bit 2
20061609
20061610
DONTC
Bit 1
DONTC
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Bit 0