AD7143ACPZ Analog Devices Inc, AD7143ACPZ Datasheet - Page 34

• Manufacturer Part Number: AD7143ACPZ
• Description: IC, CDC, 16BIT, SMD, LFCSP-16, 7143
• Manufacturer: Analog Devices Inc

Specifications of AD7143ACPZ

• Supply Voltage Range: 2.6V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 16
• Svhc: No SVHC (18-Jun-2010)
• Package / Case: LFCSP
• Base Number: 7143
• Ic Function: Programmable Controller For Capacitance Touch Sensors
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7143
REGISTER MAP
The AD7143 address space is divided into three different
register banks, referred to as Bank 1, Bank 2, and Bank 3.
Figure 47 illustrates the division of these three banks.
Bank 1 registers contain control registers, CDC conversion
control registers, interrupt enable registers, interrupt status
registers, CDC 16-bit conversion data registers, device ID
registers, and proximity status registers.
Bank 2 registers contain the configuration registers used for
uniquely configuring the CIN inputs for each conversion stage.
Initialize the Bank 2 configuration registers immediately after
power-up to obtain valid CDC conversion result data.
ADDR 0x7F0
ADDR 0x00B
ADDR 0x000
ADDR 0x001
ADDR 0x005
ADDR 0x008
ADDR 0x013
ADDR 0x017
ADDR 0x018
ADDR 0x042
ADDR 0x043
CDC 16-BIT CONVERSION DATA
PROXIMITY STATUS REGISTER
CALIBRATION AND SET UP
INVALID DO NOT ACCESS
INVALID DO NOT ACCESS
UNUSED (4 REGISTERS)
DEVICE ID REGISTER
INTERRUPT ENABLE
INTERRUPT STATUS
REGISTER BANK 1
SET UP CONTROL
(3 REGISTERS)
(8 REGISTERS)
(4 REGISTERS)
(3 REGISTERS)
(1 REGISTER)
Figure 47. Layout of Bank 1 Registers, Bank 2 Registers, and Bank 3 Registers
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x0B0
ADDR 0x0B8
ADDR 0x080
ADDR 0x088
ADDR 0x090
ADDR 0x098
Rev. 0 | Page 34 of 56
STAGE0 CONFIGURATION
STAGE1 CONFIGURATION
STAGE2 CONFIGURATION
STAGE3 CONFIGURATION
STAGE4 CONFIGURATION
STAGE5 CONFIGURATION
STAGE6 CONFIGURATION
STAGE7 CONFIGURATION
REGISTER BANK 2
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
Bank 3 registers contains the results of each conversion stage.
These registers automatically update at the end of each conversion
sequence. Although these registers are primarily used by the
AD7143 internal data processing, they are accessible by the host
processor for additional external data processing, if desired.
Default values are undefined for Bank 2 registers and Bank 3
registers until after power up and configuration of the Bank 2
registers.
ADDR 0x0E0
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x0B0
ADDR 0x0B8
ADDR 0x088
ADDR 0x090
ADDR 0x098
REGISTER BANK 3
STAGE0 RESULTS
STAGE1 RESULTS
STAGE2 RESULTS
STAGE3 RESULTS
STAGE4 RESULTS
STAGE5 RESULTS
STAGE6 RESULTS
STAGE7 RESULTS
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)