LP2992IM5-1.8 National Semiconductor, LP2992IM5-1.8 Datasheet - Page 13
![IC, LDO VOLT REG, 1.8V, 250mA, 5-SOT-23](/photos/18/97/189782/3833572_sml.gif)
LP2992IM5-1.8
Manufacturer Part Number
LP2992IM5-1.8
Description
IC, LDO VOLT REG, 1.8V, 250mA, 5-SOT-23
Manufacturer
National Semiconductor
Datasheet
1.LP2992AIM5-1.5.pdf
(16 pages)
Specifications of LP2992IM5-1.8
Primary Input Voltage
16V
Output Voltage Fixed
1.8V
Dropout Voltage Vdo
450mV
No. Of Pins
5
Output Current
250mA
Operating Temperature Range
-40°C To +125°C
Termination Type
SMD
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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ON/OFF INPUT OPERATION
The LP2992 is shut off by driving the ON/OFF input low, and
turned on by pulling it high. If this feature is not to be used,
the ON/OFF input should be tied to V
output on at all times.
To assure proper operation, the signal source used to drive
the ON/OFF input must be able to swing above and below the
specified turn-on/turn-off voltage thresholds listed in the Elec-
trical Characteristics section under V
operation, the turn-on (and turn-off) voltage signals applied to
the ON/OFF input must have a slew rate which is
≥
Caution: the regulator output voltage can not be guaranteed
if a slow-moving AC (or DC) signal is applied that is in the
range between the specified turn-on and turn-off voltages list-
ed under the electrical specification V
Characteristics).
REVERSE INPUT-OUTPUT VOLTAGE
The PNP power transistor used as the pass element in the
LP2992 has an inherent diode connected between the regu-
lator output and input. During normal operation (where the
input voltage is higher than the output) this diode is reverse-
biased.
However, if the output is pulled above the input, this diode will
turn ON and current will flow into the regulator output. In such
cases, a parasitic SCR can latch which will allow a high cur-
rent to flow into V
damage the part.
In any application where the output may be pulled above the
input, an external Schottky diode must be connected from
40 mV/µs.
IN
(and out the ground pin), which can
ON/OFF
IN
ON/OFF
to keep the regulator
. To prevent mis-
(see Electrical
13
V
verse voltage across the LP2992 to 0.3V (see Absolute Max-
imum Ratings).
LLP MOUNTING
The LLP package requires specific mounting techniques
which are detailed in National Semiconductor Application
Note # 1187. Referring to the section PCB Design Recom-
mendations, it should be noted that the pad style which
should be used with the LLP package is the NSMD (non-sol-
der mask defined) type.
The thermal dissipation of the LLP package is directly related
to the printed circuit board construction and the amount of
additional copper area.
For the LP2992 in the LDE06A 6-Lead LLP package, the
junction-to-case thermal rating, θ
case is actually the bottom of the package at the center of the
DAP. The junction-to-ambient thermal performance for the
LP2992 in the LDE06A 6-Lead LLP package, using the
JEDEC standards is summarized in the following table:
IN
2–Layer
4–Layer
to V
JEDEC
JEDEC
Board
Type
OUT
(cathode on V
Thermal
None
Vias
1
2
4
6
IN
, anode on V
19°C/W
19°C/W
19°C/W
19°C/W
19°C/W
JC
θ
, is 19°C/W, where the
JC
OUT
), to limit the re-
282°C/W
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94°C/W
78°C/W
66°C/W
62°C/W
θ
JA