SI9137LG Vishay, SI9137LG Datasheet - Page 14
![IC, PWM AND PSM CONVERTER CTRL, SSOP-28](/photos/18/99/189938/3833516_sml.gif)
SI9137LG
Manufacturer Part Number
SI9137LG
Description
IC, PWM AND PSM CONVERTER CTRL, SSOP-28
Manufacturer
Vishay
Datasheet
1.SI9137LG.pdf
(15 pages)
Specifications of SI9137LG
Primary Input Voltage
15V
No. Of Outputs
5
Output Voltage
12V
Output Current
1A
No. Of Pins
28
Operating Temperature Range
0°C To +90°C
Power Dissipation Pd
762mW
Termination Type
SMD
Duty Cycle (max)
95 %
Mounting Style
SMD/SMT
Package / Case
SSOP-28
Switching Frequency
330 KHz
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Synchronous Pin
No
Topology
Boost, Buck, Flyback
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI9137LG
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Si9137
Vishay Siliconix
DESCRIPTION OF OPERATION (CONT’D)
Current Limit: Flyback Converter
Similar to the buck converter; when the voltage across pin
CSP and pin CSN exceeds 410-mV typical, the two MOSFETs
will be turned off regardless of the input and output conditions.
Grounding:
There are two separate grounds on the Si9137, analog signal
ground (GND) and power ground (PGND). The purpose of two
separate grounds is to prevent the high currents on the power
devices (both external and internal) from interfering with the
analog signals. The internal components of Si9137 have their
grounds tied (internally) together. These two grounds are then
tied together (externally) at a single point, to ensure Si9137
noise immunity.
This separation of grounds should be maintained in the
external circuitry, with the power ground of all power devices
being returned directly to the input capacitors, and the small
signal ground being returned to the GND pin of Si9137.
RESET Power-Good Voltage Monitor
The power-good monitor generates a system RESET signal.
At first power-up (RUN/STOP going high), RESET is held low
until the 3.3-V, 5-V outputs are in regulation and beyond the
UVLO timer. At this point, an internal timer begins counting
oscillator pulses and RESET continues to be held low until
32,000 cycles have elapsed. After this timeout period, 107 ms
@ 300 kHz, RESET is actively pulled up to V
recommended 20-kW resistor to V
Output Overvoltage Protection
The 5-V and 3.3-V SMPS outputs are monitored for
overvoltage. If either output is typically more than 10% above
the nominal regulation point, all low-side gate drivers are
latched high until RUN/STOP is toggled. This action turns on
the synchronous rectifier MOSFETs with a 100% duty cycle,
in turn rapidly discharging the output capacitors and forcing all
SMPS outputs to ground.
www.vishay.com
14
L
is on the RESET pin.
L
, when the
Output Undervoltage Protection
Each of the Si9137 5-V and 3.3-V SMPS outputs has an
undervoltage protection circuit that is activated 6,144 clock
cycles (20.48 ms) after the SMPS is enabled. If either SMPS
output is typically under 70% of the nominal value, all SMPSs
are latched off and their outputs are clamped to ground by the
synchronous rectifier MOSFETs. The SMPS will not restart
until RUN/STOP is toggled.
Stability:
Buck Converters:
In order to simplify designs, the 5-V and 3.3-V supplies do not
require external frequency compensation. Meanwhile, it
achieves excellent regulation and efficiency. The converters
are current mode control, with a bandwidth substantially
higher than the LC tank dominant pole frequency of the output
filter. To ensure stability, the minimum capacitance and
maximum ESR values are:
where V
Rcs is the current sensing resistor in ohms and BW = 50 khz
With the components specified in the application circuit
(L = 10 mH,
approximately 0.1 W), the converter should have a bandwidth
of approximately 50 kHz, with minimum phase margin of 65_,
and dc gain above 50 dB.
Other Outputs
The Si9137 also provides a 3.3-V reference which can be
externally loaded up to 1 mA, as well as, a 5-V LDO output
which can be loaded up to 30 mA, or even more depending on
the system application. When the 5-V buck converter is turned
on, the 5-V LDO output is shorted with the 5-V buck converter
output, so its loading capability is substantially increased. For
stability, the 3.3-V reference output requires a 1-mF capacitor,
and the 5-V LDO output requires a 4.7-mF capacitor.
C
LOAD
w
REF
2p
= 3.3 V, V
x V
R
OUT
CS
V
REF
x
= 0.02 W,
OUT
R
CS
is the output voltage (5 V or 3.3 V),
x
BW
C
OUT
S-40808—Rev. C, 26-Apr-04
ESR v
Document Number: 70874
= 330 mF,
V
OUT
V
REF
x R
cs
ESR