PIC32MX675F512L-80I/BG Microchip Technology, PIC32MX675F512L-80I/BG Datasheet - Page 89

• Manufacturer Part Number: PIC32MX675F512L-80I/BG
• Description: IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX675F512L-80I/BG

• Controller Family/series: PIC32
• Ram Memory Size: 64KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 32 Bit
• Program Memory Size: 512 KB
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 4-19:
Legend:
Note
35F0 DCH7SSIZ
3600 DCH7DSIZ
3610 DCH7SPTR
3620 DCH7DPTR
3630 DCH7CSIZ
3640 DCH7CPTR
3650
1:
DCH7DAT
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
DMA CHANNELS 0-7 REGISTER MAP
31/15
—
—
—
—
—
—
—
—
30/14
—
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
—
28/12
—
—
—
—
—
—
—
—
27/11
—
—
—
—
—
—
—
—
(1,2)
26/10
(CONTINUED)
—
—
—
—
—
—
—
—
25/9
—
—
—
—
—
—
—
—
24/8
CHSPTR<15:0>
CHDPTR<15:0>
CHCPTR<15:0>
CHSSIZ<15:0>
CHDSIZ<15:0>
CHCSIZ<15:0>
—
—
—
—
—
—
—
—
Bits
23/7
—
—
—
—
—
—
—
22/6
—
—
—
—
—
—
—
21/5
—
—
—
—
—
—
—
20/4
Section 12.1.1 “CLR, SET and INV Registers”
CHPDAT<7:0>
—
—
—
—
—
—
—
19/3
—
—
—
—
—
—
—
18/2
—
—
—
—
—
—
—
17/1
—
—
—
—
—
—
—
for more
16/0
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000