ATTINY84V-10PU Atmel, ATTINY84V-10PU Datasheet - Page 121

• Manufacturer Part Number: ATTINY84V-10PU
• Description: AVR MCU, 8K FLASH, 512B RAM, 512B EE
• Manufacturer: Atmel

Specifications of ATTINY84V-10PU

• Controller Family/series: AVR Tiny
• No. Of I/o's: 12
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 10MHz
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-14
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.1
15.1.1
8006F–AVR–02/07
Register Description
GTCCR – General Timer/Counter Control Register
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 15-2. Prescaler for Timer/Counter0
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted.
This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-
ing during configuration. When the TSM bit is written to zero, the PSR10 bit is cleared by
hardware, and the Timer/Counter start counting.
• Bit 0 – PSR10: Prescaler 0 Reset Timer/Counter n
When this bit is one, the Timer/Countern prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set.
Bit
0x23 (0x43)
Read/Write
Initial Value
1. The synchronization logic on the input pins (
PSR10
clk
T0
I/O
TSM
R/W
7
0
Synchronization
ExtClk
R
6
–
0
< f
clk_I/O
Clear
/2) given a 50/50% duty cycle. Since the edge detector uses
R
5
–
0
R
4
–
0
T0)
is shown in
R
3
–
0
R
2
–
0
clk
Figure 15-1 on page
T0
ATtiny24/44/84
R
1
–
0
PSR10
clk_I/O
R/W
0
0
120.
/2.5.
GTCCR
121