PIC32MX440F128L-80I/BG Microchip Technology, PIC32MX440F128L-80I/BG Datasheet - Page 14

• Manufacturer Part Number: PIC32MX440F128L-80I/BG
• Description: IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F128L-80I/BG

• Controller Family/series: PIC32
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI, USB
• No. Of Pwm Channels: 5
• Core Size: 32 Bit
• Program Memory Size: 128 KB
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Embedded Interface Type: EUSART, I2C, SPI, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EUART, I2C, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARD
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC32MX3XX/4XX
44. Module: Output Compare
45. Module: Oscillator
46. Module: UART
DS80440D-page 14
If firmware clears a PWM Fault while a Fault con-
dition is asserted, an interrupt will not be
generated for the current Fault.
Work around
Firmware must poll the OCFLT bit to determine if a
Fault condition still exists.
Affected Silicon Revisions
Clock switching and Two-Speed Start-up may
cause a general exception when the reserved bit 8
of the DDPCON register is ‘0’.
Work around
Ensure that the reserved bit 8 of the DDPCON reg-
ister to set to ‘1’. For example, DDPCON = 0x100.
Affected Silicon Revisions
The RXDA bit does not correctly reflect the RX
FIFO status after an overrun event.
Work around
1. Clear the OERR bit. The FIFO pointer will be
2. If the contents of the FIFO are required, they
3. Clear the OERR bit. The FIFO pointer will be
Affected Silicon Revisions
B2
B2
B2
X
X
X
reset and the RXDA bit will reflect the current
FIFO status.
can be read by reading the UxRXREG register
four times. There are no status bits that will
correctly reflect when the last valid data was
read.
reset and the RXDA will reflect the current
FIFO status.
B3
B3
B3
X
X
X
B4
B4
B4
X
X
X
B6
B6
B6
X
X
X
47. Module: DMA
48. Module: Oscillator
49. Module: JTAG
50. Module: Oscillator
In Pattern Match mode, the DMA module may not
append all of the CRC results to the result buffer.
Work around
Use firmware to read the CRC result and append
it to the result buffer.
Affected Silicon Revisions
Clock source switching may cause a general
exception or a POR when switching from a slow
clock to a fast clock.
Work around
Clock source switches should be performed by
first switching to the FRC, and then switching to
the target clock source.
Affected Silicon Revisions
On 64-pin devices, an external pull-up resistor is
required on the TMS pin for proper JTAG.
Work around
Connect a 100k-200k pull-up to the TMS pin.
Affected Silicon Revisions
Changing the PB divisor on the fly may generate
exceptions.
Work around
Ensure 8 NOP instructions precede the write to the
PBDIV bits and 8 NOP instructions follow the write
to the PBDIV bits.
Affected Silicon Revisions
B2
B2
B2
B2
X
X
X
X
B3
B3
B3
B3
X
X
X
X
B4
B4
B4
B4
X
X
X
X
© 2010 Microchip Technology Inc.
B6
B6
B6
B6
X
X
X
X