PIC32MX360F256L-80I/BG Microchip Technology, PIC32MX360F256L-80I/BG Datasheet - Page 53

• Manufacturer Part Number: PIC32MX360F256L-80I/BG
• Description: IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F256L-80I/BG

• Controller Family/series: PIC32
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• No. Of Pwm Channels: 5
• Core Size: 32 Bit
• Program Memory Size: 256 KB
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Embedded Interface Type: EUSART, I2C, SPI
• Rohs Compliant: Yes
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EUART, I2C, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARD
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 4-22:
TABLE 4-23:
TABLE 4-24:
Legend:
Note
BFC0_2FF0 DEVCFG3
BFC0_2FF4 DEVCFG2
BFC0_2FF8 DEVCFG1
BFC0_2FFC DEVCFG0
Legend:
Note
Legend:
BF80_0220 RTCTIME
BF80_0230 RTCDATE
BF80_0240 ALRMTIME
BF80_0250 ALRMDATE
BF80_F220
Virtual
Virtual
Virtual
Addr
Addr
Addr
SFR
SFR
SFR
1:
1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These bits are only available on PIC32MX4XX devices.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Name
Name
Name
DEVID
SFR
SFR
SFR
RTCC REGISTERS MAP
DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
DEVICE AND REVISION ID SUMMARY
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0 USERID15 USERID14 USERID13 USERID12 USERID11 USERID10 USERID9 USERID8 USERID7 USERID6 USERID5 USERID4 USERID3 USERID2 USERID1 USERID0
15:0 FUPLLEN
15:0
15:0
15:0
PWP15
31/15
31/15
31/15
Bits
Bits
Bits
—
—
—
—
—
FCKSM<1:0>
(1)
PWP14
30/14
30/14
30/14
Bits
Bits
Bits
YEAR10<3:0>
—
—
—
—
—
—
SEC10<3:0>
DAY10<3:0>
SEC10<3:0>
DAY10<3:0>
MIN10<3:0>
HR10<3:0>
VER<3:0>
PWP13
29/13
29/13
29/13
Bits
Bits
Bits
—
—
—
—
—
FPBDIV<1:0>
—
(1)
(CONTINUED)
PWP12
28/12
28/12
28/12
Bits
Bits
Bits
CP
—
—
—
—
—
27/11
27/11
27/11
Bits
Bits
Bits
—
—
—
—
—
—
—
—
IOFNC
26/10
26/10
26/10
OSC
Bits
Bits
Bits
YEAR01<3:0>
—
—
—
—
—
—
SEC01<3:0>
DAY01<3:0>
SEC01<3:0>
DAY01<3:0>
MIN01<3:0>
HR01<3:0>
FUPLLIDIV<2:0>
Bits
25/9
Bits
25/9
Bits
25/9
POSCMD<1:0>
—
—
—
—
—
—
(1)
BWP
Bits
24/8
Bits
24/8
Bits
24/8
—
—
—
—
—
DEVID<15:0>
FWDTEN
IESO
23/7
23/7
23/7
Bits
Bits
Bits
—
—
—
—
—
—
—
—
—
Bits
22/6
MONTH10<3:0>
MONTH10<3:0>
Bits
22/6
Bits
22/6
DEVID<27:16>
—
—
—
—
—
—
—
—
—
—
MIN10<3:0>
MIN10<3:0>
FPLLMULT<2:0>
FSOSCEN
Bits
21/5
Bits
21/5
Bits
21/5
—
—
—
—
—
—
—
—
—
20/4
20/4
20/4
Bits
Bits
Bits
—
—
—
—
—
—
—
—
—
ICESEL
PWP19
Bits
19/3
Bits
19/3
Bits
19/3
—
—
—
—
—
—
WDTPS<4:0>
PWP18
Bits
18/2
MONTH01<3:0>
MONTH01<3:0>
Bits
18/2
Bits
18/2
WDAY01<3:0>
WDAY01<3:0>
—
—
—
—
MIN01<3:0>
MIN01<3:0>
FPLLODIV<2:0>
FPLLIDIV<2:0>
FNOSC<2:0>
PWP17
17/1
17/1
17/1
Bits
Bits
Bits
—
—
—
DEBUG<1:0>
PWP16
16/0
16/0
16/0
Bits
Bits
Bits
—
—
—