PIC24FJ256GB210-I/BG Microchip Technology, PIC24FJ256GB210-I/BG Datasheet - Page 145
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PIC24FJ256GB210-I/BG
Manufacturer Part Number
PIC24FJ256GB210-I/BG
Description
IC, 16BIT MCU, PIC24F, 32MHZ, BGA-121
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Specifications of PIC24FJ256GB210-I/BG
Controller Family/series
PIC24
No. Of I/o's
84
Ram Memory Size
96KB
Cpu Speed
32MHz
No. Of Timers
5
No. Of Pwm Channels
9
Core Size
16 Bit
Program Memory Size
256KB
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
96 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
44
Number Of Timers
5
Operating Supply Voltage
2.2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001, MA240021
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ256GB210-I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
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FIGURE 8-2:
8.5.1
The system clock is generated from the 96 MHz branch
using a configurable postscaler/divider to generate a
range of frequencies for the system clock multiplexer.
The output of the multiplexer is further passed through
a fixed divide-by-3 divider and the final output is used
TABLE 8-2:
2010 Microchip Technology Inc.
Note 1:
(4 MHz or
8 MHz)
Input from
POSC
Input from
FRC
FNOSC<2:0>
These options are not compatible with USB operation. They may be used whenever the PLL branch is
selected and the USB module is disabled.
SYSTEM CLOCK GENERATION
SYSTEM CLOCK OPTIONS FOR 96 MHz PLL BLOCK
MCU Clock Division
(CPDIV<1:0>)
96 MHz PLL BLOCK
None (00)
2 (01)
4 (10)
8 (11)
12
8
6
5
4
3
2
1
PLLDIV<2:0>
111
110
101
100
011
010
001
000
4 MHz
PIC24FJ256GB210 FAMILY
96 MHz
PLL
as the system clock. Figure 8-2 shows this logic in the
system clock sub-block. Since the source is a 96 MHz
signal, the possible system clock frequencies are listed
in Table 8-2. The available system clock options are
always the same, regardless of the setting of the
PLLDIV Configuration bits.
2
3
32 MHz
(Instruction Rate in MIPS)
System Clock Frequency
32 MHz (16)
8 MHz (4)
4 MHz (2)
16 MHz (8)
8
4
2
1
CPDIV<1:0>
(1)
(1)
11
10
01
00
DS39975A-page 145
PLL Output
for System Clock
48 MHz Clock
for USB Module
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