PIC16F1826-I/MV Microchip Technology, PIC16F1826-I/MV Datasheet - Page 333

• Manufacturer Part Number: PIC16F1826-I/MV
• Description: IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1826-I/MV

• Controller Family/series: PIC16F
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 32MHz
• No. Of Timers: 3
• Interface: EUSART, I2C, SPI
• Core Size: 8 Bit
• Program Memory Size: 2kWords
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-UFQFN Exposed Pad
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 KB
• Interface Type: MI2C, SPI, EUSART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28.2
ADDFSR
Syntax:
Operands:
Operation:
Status Affected:
Description:
ADDLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
ADDWFC
Syntax:
Operands:
Operation:
Status Affected:
Description:
 2010 Microchip Technology Inc.
Instruction Descriptions
Add W and f
[ label ] ADDWF
0  f  127
d 0,1
(W) + (f)  (destination)
C, DC, Z
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
ADD W and CARRY bit to f
[ label ] ADDWFC
0  f  127
d [0,1]
(W) + (f) + (C)  dest
C, DC, Z
Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
[ label ] ADDFSR FSRn, k
n  [ 0, 1]
FSR(n) + k  FSR(n)
the contents of the FSRnH:FSRnL
register pair.
FSRn is limited to the range 0000h -
FFFFh. Moving beyond these bounds
will cause the FSR to wrap around.
[ label ] ADDLW
0  k  255
(W) + k  (W)
The contents of the W register are
added to the eight-bit literal ‘k’ and the
result is placed in the W register.
Add Literal to FSRn
-32  k  31
None
The signed 6-bit literal ‘k’ is added to
Add literal and W
C, DC, Z
f,d
k
f {,d}
Preliminary
ANDLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
ASRF
Syntax:
Operands:
Operation:
Status Affected:
Description:
PIC16F/LF1826/27
AND W with f
[ label ] ANDWF
0  f  127
d 0,1
(W) .AND. (f)  (destination)
Z
AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
AND literal with W
[ label ] ANDLW
0  k  255
(W) .AND. (k)  (W)
Z
The contents of W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W register.
Arithmetic Right Shift
[ label ] ASRF
0  f  127
d [0,1]
(f<7>) dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
C, Z
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in reg-
ister ‘f’.
register f
f {,d}
DS41391C-page 333
f,d
k
C