FM24C64-G Ramtron, FM24C64-G Datasheet - Page 6

• Manufacturer Part Number: FM24C64-G
• Description: IC, FRAM, 64KBIT, 1MHZ, SOIC-8
• Manufacturer: Ramtron

Specifications of FM24C64-G

• Memory Size: 64Kbit
• Memory Configuration: 8K X 8
• Ic Interface Type: 2 Wire, Serial
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read Operation
There are two basic types of read operations. They
are current address read and selective address read. In
a current address read, the FM24C64 uses the internal
address latch to supply the address. In a selective
read, the user performs a procedure to set the address
to a specific value.
Current Address & Sequential Read
The FM24C64 uses an internal latch to supply the
address for a read operation. A current address read
uses the existing value in the address latch as a
starting place for the read operation. The system
reads from the address immediately following that of
the last operation.
To perform a current address read, the bus master
supplies a device address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving the complete device address, the FM24C64
will begin shifting out data from the current address
on the next clock. The current address is the value
held in the internal address latch. Beginning with the
current address, the bus master can read any number
of bytes. Thus, a sequential read is simply a current
address read with multiple byte transfers. After each
byte the internal address counter will be incremented.
Each time the bus master acknowledges a byte, this
indicates that the FM24C64 should read out the next
sequential byte.
There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
likely create a bus contention as the FM24C64
Rev. 3.2
Feb. 2011
By FM24C64
By Master
By FM24C64
By Master
Start
S
DEVICE ADDRESS
Start
S
DEVICE ADDRESS
0
A
X X X
ADDRESS MSB
0
Figure 6. Multiple Byte Write
Address and Data
A
X X X
ADDRESS MSB
Figure 5. Byte Write
Address and Data
A
ACKNOWLEDGE
ADDRESS LSB
A
attempts to read out additional data onto the bus. The
four valid methods are:
1.
2.
3.
4.
If the internal address reaches 1FFFh, it will wrap
around to 0000h on the next read cycle. Figures 7 and
8 show the proper operation for current address reads.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
three bytes of a write operation to set the internal
address followed by subsequent read operations.
To perform a selective read, the bus master sends out
the device address with the LSB set to 0. This
specifies a write operation. According to the write
protocol, the bus master then sends the address bytes
that are loaded into the internal address latch. After
the FM24C64 acknowledges the address, the bus
master issues a start condition. This simultaneously
aborts the write operation and allows the read
command to be issued with the device address LSB
set to a 1. The operation is now a current address
read.
ACKNOWLEDGE
The bus master issues a no-acknowledge in the
9
This is illustrated in Figures 7-9. This is the
preferred method.
The bus master issues a no-acknowledge in the
9
The bus master issues a stop in the 9
cycle.
The bus master issues a start in the 9
cycle.
ADDRESS LSB
th
th
clock cycle and a start in the 10
clock cycle and a stop in the 10
A
DATA BYTE
A
DATA BYTE
A
DATA BYTE
A P
th
Stop
th
.
clock cycle.
FM24C64
th
th
A
Stop
6 of 12
clock
clock
P