S29AL032D70TFI030 Spansion Inc., S29AL032D70TFI030 Datasheet - Page 4

• Manufacturer Part Number: S29AL032D70TFI030
• Description: IC, FLASH, 32MBIT, 70NS, TSOP-48
• Manufacturer: Spansion Inc.

Specifications of S29AL032D70TFI030

• Memory Type: Flash
• Memory Size: 32Mbit
• Memory Configuration: 4M X 8 / 2M X 16
• Ic Interface Type: CFI, Parallel
• Access Time: 70ns
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description
S29AL032D Features
2
The S29AL032D is a 32-megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits
each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ0-DQ15; byte mode data appears on
DQ0-DQ7. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and
can also be programmed in standard EPROM programmers.
The device is available with access times as fast as 70 ns. The devices are offered in 40-pin TSOP, 48-pin
TSOP and 48-ball FBGA packages. Standard control pins- chip enable (CE#), write enable (WE#), and output
enable (OE#)-control normal read and write operations, and avoid bus contention issues.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally
generated and regulated voltages are provided for the pro-gram and erase operations.
The Secured Silicon Sector is an extra sector capable of being permanently locked by Spansion or
customers. The Secured Silicon Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked,
and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory
locked part. Note that the S29AL032D has a Secured Silicon Sector size of 128 words (256 bytes).
Factory locked parts provide several options. The Secured Silicon Sector may store a secure, random 16
byte ESN (Electronic Serial Number), customer code (programmed through the Spansion programming
service), or both.
The S29AL032D is entirely command set compatible with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using standard microprocessor write timings. Register
contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and erase operations. Reading
data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write
cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin,
or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been
completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low V
during power transitions. The hardware sector protection feature disables both program and erase
operations in any combination of the sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is not selected for erasure. True background erase can
thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses are stable for a specified amount of time, the
device enters the automatic sleep mode. The system can also place the device into the standby mode.
Power consumption is greatly reduced in both these modes.
The Spansion Flash technology combines years of Flash memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot-electron
injection.
S29AL032D
D a t a
CC
S h e e t
detector that automatically inhibits write operations
S29AL032D_00_A9 January 19, 2007