S29AL008J70TFI010 Spansion Inc., S29AL008J70TFI010 Datasheet - Page 14

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S29AL008J70TFI010

Manufacturer Part Number
S29AL008J70TFI010
Description
IC, FLASH, 8MBIT, 70NS, TSOP-48
Manufacturer
Spansion Inc.
Datasheet

Specifications of S29AL008J70TFI010

Memory Type
Flash
Memory Size
8Mbit
Memory Configuration
1M X 8 / 512K X 16
Ic Interface Type
CFI, Parallel
Access Time
70ns
Supply Voltage Range
2.7 To 3.6 V
Memory Case Style
TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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7.
7.1
7.2
14
Device Bus Operations
Word/Byte Configuration
Requirements for Reading Array Data
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the device.
inputs and control levels they require, and the resulting output. The following subsections describe each of
these operations in further detail.
Legend
L = Logic Low = V
Notes
1. Address In = Amax:A0 in WORD mode (BYTE#=V
2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment.
3. If WP# = V
4. D
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word
configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15–DQ0 are active and
controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
To read array data from the outputs, the system must drive the CE# and OE# pins to V
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at V
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
Read
Write
Standby
Output Disable
Reset
Sector Group Protect
(2) (3)
Sector Group
Unprotect
Temporary Sector
Group Unprotect
to A12 in both WORD mode and BYTE mode.
Protection/Unprotection on page 19.
depends on whether the sector was last protected or unprotected using the method described in
Unprotection on page
IN
Operation
or D
(2) (3)
OUT
IL
IH
, the outermost sector remains protected (determined by device configuration). If WP# = V
as required by command sequence, data polling, or sector group protection algorithm.
. The BYTE# pin determines whether the device outputs array data in words or bytes.
IL;
H = Logic High = V
19. The WP# contains an internal pull-up; when unconnected, WP is at V
V
0.3 V
CE#
CC
X
X
L
L
L
L
L
±
OE#
H
X
H
X
H
H
X
L
IH;
Table 7.1 S29AL008J Device Bus Operations
WE#
V
ID
H
X
H
X
X
L
L
L
= 8.5 V to 12.5 V; X = Don’t Care; A
RESET#
S29AL008J
V
0.3 V
V
V
V
CC
H
H
H
L
IH
ID
ID
ID
), Address In = Amax:A-1 in BYTE mode (BYTE#=V
±
D a t a
(Note 3)
WP#
X
X
X
X
H
H
H
S h e e t
Sector Address,
Sector Address,
A1 = H, A0 = L
A1 = H, A0 = L
A3 = A2 = L,
A3 = A2 = L,
Addresses
(Note 1)
A6 = H,
Table 7.1
A6 = L,
A
A
A
X
X
X
IN
IN
IN
IN
= Address In; D
lists the device bus operations, the
S29AL008J_00_09 February 23, 2010
(Note 4)
(Note 4)
(Note 4)
(Note 4)
High-Z
High-Z
High-Z
DQ0–
D
DQ7
OUT
IH
Section 7.10, Sector Group Protection/
OUT
.
= Data Out
(Note 4)
(Note 4)
IH
BYTE#
High-Z
High-Z
High-Z
D
= V
, the outermost sector protection
IL
OUT
X
X
). Sector addresses are Amax
IH
IL
. CE# is the power
DQ8–DQ15
DQ8–DQ14 = High-Z,
DQ15 = A-1
See Sector Group
BYTE#
High-Z
High-Z
High-Z
High-Z
= V
X
X
IL

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