AM29F800BB-55EF Spansion Inc., AM29F800BB-55EF Datasheet - Page 13

• Manufacturer Part Number: AM29F800BB-55EF
• Description: IC, FLASH, 8MBIT, 55NS, TSOP-48
• Manufacturer: Spansion Inc.

Specifications of AM29F800BB-55EF

• Memory Type: Flash
• Memory Size: 8Mbit
• Memory Configuration: 1M X 8 / 512K X 16
• Access Time: 55ns
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Legend:
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE or CE pulse.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse.
SA = Address of the sector to be erased. Address bits A18–A12 uniquely select any sector.
Notes:
1. All values are in hexadecimal.
2. See Tables 1 and 2 for description of bus operations.
3. The data is 00H for an unprotected sector group and 01H for a protected sector group. The complete bus address is
4. Read and program functions in non-erasing sectors are allowed in the Erase Suspend mode.
5. Address bits A18–A11 are don’t care for unlock and command cycles.
8/18/97
Reset/Read
Autoselect
Manufacturer ID
Autoselect
Device ID
(Top Boot Block)
Autoselect
Device ID
(Bottom Boot
Block)
Autoselect
Sector Protect
Verify (Note 3)
Byte Program
Chip Erase
Sector Erase
Erase Suspend
(Note 4)
Erase Resume
composed of the sector address (A18–A12), A1 = 1, and A0 = 0.
Read/Reset
Command
Sequence
(Note 2)
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Cycles
Write
Req’d
Bus
1
3
3
3
3
4
6
6
1
1
Addr
XXX
AAA
AAA
AAA
AAA
XXX
XXX
AAA
AAA
AAA
555
555
555
555
555
555
555
Write Cycle
First Bus
Table 7. Am29F800 Command Definitions
XXAA
XXAA
XXAA
XXAA
XXAA
XXAA
XXAA
XXB0
XXF0
XX30
Data
AA
AA
AA
AA
AA
AA
AA
F0
B0
30
P R E L I M I N A R Y
Am29F800T/Am29F800B
Addr
2AA
2AA
2AA
2AA
2AA
2AA
2AA
555
555
555
555
555
555
555
Second Bus
RA
Read/Write
Cycle
XX55
XX55
XX55
XX55
XX55
XX55
XX55
Data
RD
55
55
55
55
55
55
55
Third Bus Write
Addr
AAA
AAA
AAA
AAA
AAA
AAA
AAA
555
555
555
555
555
555
555
Cycle
XX90
XX90
XX90
XX90
XXA0
XX80
XX80
Data
A0
90
90
90
90
80
80
XX00
XX01
XX01
Addr
(SA)
(SA)
X02
X04
AAA
AAA
Fourth Bus
555
555
Read/Write
PA
00
02
02
Cycle
XXAA
XXAA
XX01
22D6
XX00
XX01
2258
Data
PD
AA
AA
D6
01
58
00
01
Addr
2AA
2AA
Write Cycle
555
555
Fifth Bus
XX55
XX55
Data
55
55
Addr
AAA
Write Cycle
555
SA
Sixth Bus
XX10
XX30
Data
10
30
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