25LC1024-I/ST Microchip Technology, 25LC1024-I/ST Datasheet - Page 11

• Manufacturer Part Number: 25LC1024-I/ST
• Description: IC, EEPROM, 1MBIT, SERIAL, 20MHZ TSSOP-8
• Manufacturer: Microchip Technology

Specifications of 25LC1024-I/ST

• Memory Size: 1Mbit
• Ic Interface Type: SPI
• Clock Frequency: 20MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: TSSOP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Memory Configuration: 128K X 8

2.4
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2:
The Write-In-Process (WIP) bit indicates whether the
25LC1024 is busy with a write operation. When set to
a ‘
is in progress. This bit is read-only.
FIGURE 2-6:
© 2008 Microchip Technology Inc.
W/R
WPEN
W/R = writable/readable. R = read-only.
SCK
1
CS
SO
’, a write is in progress, when set to a ‘
7
SI
Read Status Register Instruction
(RDSR)
6
–
X
0
X
5
–
0
STATUS REGISTER
X
4
–
0
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
1
High-Impedance
W/R
BP1
3
0
Instruction
2
W/R
BP0
0
2
3
0
WEL
4
R
1
0
’, no write
1
5
WIP
R
0
0
6
1
7
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘
‘
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile and are shown in Table 2-3.
See Figure 2-6 for the RDSR timing sequence.
7
0
8
’, the latch prohibits writes to the array. The state of
1
’, the latch allows writes to the array, when set to a
6
9
Data from STATUS register
10
5
11
4
12
3
25LC1024
13
2
14
1
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0