HN58C256AP85E Renesas Electronics America, HN58C256AP85E Datasheet - Page 17
![IC, EEPROM, 256KBIT, 1MHZ, DIP-28](/photos/19/5/190505/4467765_sml.jpg)
HN58C256AP85E
Manufacturer Part Number
HN58C256AP85E
Description
IC, EEPROM, 256KBIT, 1MHZ, DIP-28
Manufacturer
Renesas Electronics America
Datasheet
1.HN58C256AP85E.pdf
(26 pages)
Specifications of HN58C256AP85E
Memory Size
256Kbit
Memory Configuration
32K X 8
Ic Interface Type
Parallel
Access Time
85ns
Supply Voltage Range
4.5V To 5.5V
Memory Case Style
DIP
No. Of Pins
28
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
HN58C256A Series, HN58C257A Series
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle.
Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE. When
CE or WE is high for 100 µs after data input, the EEPROM enters write mode automatically and the input
data are written into the EEPROM.
Data Polling
Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read mode
during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the EEPROM is
performing a write operation.
RDY/Busy Signal (only the HN58C257A series)
RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high
impedance except in write cycle and is lowered to V
after the first write signal. At the end of a write cycle,
OL
the RDY/Busy signal changes state to high impedance.
RES Signal (only the HN58C257A series)
When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping
RES low when V
is switched. RES should be high during read and programming because it doesn't provide
CC
a latch function.
V
CC
Read inhibit
Read inhibit
RES
Program inhibit
Program inhibit
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising
edge of WE or CE.
Rev.6.00, Oct. 26.2006, page 17 of 24