CAT93C66VI-G CATALYST SEMICONDUCTOR, CAT93C66VI-G Datasheet
CAT93C66VI-G
Specifications of CAT93C66VI-G
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CAT93C66VI-G Summary of contents
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CAT93C66 4 kb Microwire Serial CMOS EEPROM Description The CAT93C66 CMOS Serial EEPROM device which is organized as either 256 registers of 16 bits (ORG pin at V registers of 8 bits (ORG pin at GND). ...
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MARKING DIAGRAMS A = Assembly Location Code 3 = Mark “3” for (lead finish Matte−Tin) A3G G = Product Revision: Fixed as “G” 93C66XT 93C66X = Specific Device Code YMXXXX T = Temperature Range Y = Production Year (Last Digit) ...
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Table 1. PIN FUNCTION Pin Name CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output Table 2. ABSOLUTE MAXIMUM RATINGS Storage Temperature Voltage on Any Pin with Respect to Ground (Note 1) Stresses exceeding Maximum ...
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Table 5. PIN CAPACITANCE (T = 25° 1.0 MHz Symbol C (Note 4) Output Capacitance (DO) OUT C (Note 4) Input Capacitance (CS, SK, DI, ORG These parameters are tested initially and after a ...
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Table 8. A.C. TEST CONDITIONS Input Rise and Fall Times ≤ Input Pulse Voltages 0 2.4 V Timing Reference Voltages 0.8 V, 2.0 V Input Pulse Voltages 0.2 V Timing Reference Voltages 0.5 V Output Load ...
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Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C66 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out ...
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Write After receiving a WRITE command (Figure 5), address and the data, the CS (Chip Select) pin must be deselected for a minimum The falling edge of CS will start the CSMIN self clocking clear and data ...
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Erase All Upon receiving an ERAL command (Figure 7), the CS (Chip Select) pin must be deselected for a minimum The falling edge of CS will start the self clocking CSMIN clear cycle of all memory locations ...
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PIN # 1 IDENTIFICATION D TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL ...
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PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...
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PIN#1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O SYMBOL ...
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E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...
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D E PIN#1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A2 0.45 0.55 A3 0.20 REF b 0.20 0.25 D 1.90 2.00 D2 1.30 1.40 E 2.90 3.00 E2 1.20 1.30 e 0.50 TYP ...
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D e PIN #1 IDENTIFICATION TOP VIEW θ1 b θ2 SIDE VIEW Notes: (1) All dimensions in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-178. PACKAGE DIMENSIONS SOT−23, 6 Lead CASE 527AJ−01 ISSUE O SYMBOL ...
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... The standard lead finish is NiPdAu. 11. The device used in the above example is a CAT93C66VI−GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel, 3,000 units/Reel). 12. For SOIC, EIAJ (X) package the standard lead finish is Matte−Tin. This package is available in 2,000 pcs/reel, i.e. CAT93C66XI−T2. ...