CAT93C56VI-GT3 CATALYST SEMICONDUCTOR, CAT93C56VI-GT3 Datasheet - Page 8

• Manufacturer Part Number: CAT93C56VI-GT3
• Description: IC, EEPROM, 2KBIT, SERIAL, 2MHZ, SOIC-8
• Manufacturer: CATALYST SEMICONDUCTOR

Specifications of CAT93C56VI-GT3

• Memory Size: 2Kbit
• Memory Configuration: 256 X 8 / 128 X 16
• Ic Interface Type: Microwire
• Clock Frequency: 2MHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Write
and the data, the CS (Chip Select) pin must be deselected for
a minimum of t
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the SK
pin is not necessary after the device has entered the self
clocking mode. The ready/busy status of the CAT93C56/57
can be determined by selecting the device and polling the
DO pin. Since this device features Auto−Clear before write,
it is NOT necessary to erase a memory location before it is
written into.
After receiving a WRITE command (Figure 5), address
DO
DO
CS
CS
SK
SK
DI
DI
CSMIN
1
1
. The falling edge of CS will start the
1
0
1
1
A
N
A
N
A
N−1
A
N−1
HIGH−Z
Figure 6. Erase Instruction Timing
Figure 5. Write Instruction Timing
HIGH−Z
http://onsemi.com
A
0
8
A
D
0
N
Erase
(Chip Select) pin must be deasserted for a minimum of
t
clocking clear cycle of the selected memory location. The
clocking of the SaK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Once cleared, the content of a
cleared location returns to a logical “1” state.
CSMIN
Upon receiving an ERASE command and address, the CS
(Figure 6). The falling edge of CS will start the self
D
0
t
SV
t
SV
t
EW
STATUS VERIFY
t
t
EW
CSMIN
BUSY
t
CS
VERIFY
STATUS
BUSY
READY
READY
HIGH−Z
STANDBY
t
STANDBY
HZ
HIGH−Z
t
HZ