DS92LV010ATM National Semiconductor, DS92LV010ATM Datasheet - Page 8

• Manufacturer Part Number: DS92LV010ATM
• Description: IC, 1BIT BUS TRANSCEIVER, SOIC-8
• Manufacturer: National Semiconductor

Specifications of DS92LV010ATM

• Output Current: 2mA
• No. Of Channels: 1
• Input Level: 2V
• Logic Case Style: SOIC
• No. Of Pins: 8
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Logic Type: Bus Transceiver
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Application Information
There are a few common practices which should be implied
when designing PCB for BLVDS signaling. Recommended
practices are:
•
•
•
•
•
Use at least 4 layer PCB board (BLVDS signals, ground,
power and TTL signals).
Keep drivers and receivers as close to the (BLVDS port
side) connector as possible.
Bypass each BLVDS device and also use distributed bulk
capacitance. Surface mount capacitors placed close to
power and ground pins work best. Two or three multi-layer
ceramic (MLC) surface mount capacitors (0.1 µF, and 0.01
µF in parallel should be used between each V
ground. The capacitors should be as close as possible to
the V
Use the termination resistor which best matches the
differential impedance of your transmission line.
Leave unused LVDS receiver inputs open (floating)
LOOP BACK MODE
MODE SELECTED
TRI-STATE MODE
RECEIVER MODE
DRIVER MODE
CC
Pin Name
DO±/RI±
pin.
R
GND
DIN
V
RE
DE
OUT
CC
TABLE 1. Functional Table
Pin #
6, 7
2
3
5
1
4
8
DE
H
H
L
L
Input/Output
TABLE 4. Device Pin Descriptions
CC
RE
I/O
NA
NA
H
H
L
L
O
and
I
I
I
8
TTL Driver Input
LVDS Driver Outputs/LVDS Receiver Inputs
TTL Receiver Output
Receiver Enable TTL Input (Active Low)
Driver Enable TTL Input (Active High)
Ground
Power Supply
L = Low state
H = High state
X = High or Low logic state
Z = High impedance state
L = Low state
H = High state
RE
DE
H
L
L
L
H
H
H
L
INPUTS
2 > & > 0.8
TABLE 2. Transmitter Mode
TABLE 3. Receiver Mode
100 mV > & > −100 mV
Description
DI
H
X
L
INPUTS
H (> +100 mV)
L (< −100 mV)
(RI+)-(RI−)
X
DO+
H
L
X
Z
OUTPUTS
DO−
H
L
X
Z
OUTPUT
H
X
L
Z