XC9536-15VQG44C Xilinx Inc, XC9536-15VQG44C Datasheet - Page 6

CMOS ISP FLASH CPLD, 9536, VQFP44

XC9536-15VQG44C

Manufacturer Part Number
XC9536-15VQG44C
Description
CMOS ISP FLASH CPLD, 9536, VQFP44
Manufacturer
Xilinx Inc
Series
XC9500r

Specifications of XC9536-15VQG44C

Cpld Type
FLASH
No. Of Macrocells
36
No. Of I/o's
34
Propagation Delay
15ns
Global Clock Setup Time
8ns
Frequency
95.2MHz
Supply Voltage Range
4.75V To 5.25V
Operating
RoHS Compliant
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
15.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
2
Number Of Macrocells
36
Number Of Gates
800
Number Of I /o
34
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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XC9500 In-System Programmable CPLD Family
All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in
originates from either of three global clocks or a product
6
I/O/GCK2
I/O/GCK3
I/O/GCK1
I/O/GSR
Figure
4, the macrocell register clock
Figure 4: Macrocell Clock and Set/Reset Capability
Product Term Set
Product Term Clock
Product Term Reset
Global Set/Reset
Global Clock 1
Global Clock 2
Global Clock 3
www.xilinx.com
term clock. Both true and complement polarities of a GCK
pin can be used within the device. A GSR input is also pro-
vided to allow user registers to be set to a user-defined
state.
DS063 (v5.5) June 25, 2007
D/T
S
R
Product Specification
Macrocell
DS063_04_110501
R

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