M4A5-128/64-10YC LATTICE SEMICONDUCTOR, M4A5-128/64-10YC Datasheet - Page 21
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M4A5-128/64-10YC
Manufacturer Part Number
M4A5-128/64-10YC
Description
IC, MACH4 ISP EEPLD, PQFP100, 5.25V
Manufacturer
LATTICE SEMICONDUCTOR
Series
IspMACH 4Ar
Datasheet
1.M4A5-12864-10YC.pdf
(61 pages)
Specifications of M4A5-128/64-10YC
No. Of Macrocells
128
No. Of I/o's
64
Propagation Delay
10ns
Frequency
100MHz
Supply Voltage Range
4.75V To 5.25V
Operating Temperature Range
0°C To +70°C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M4A5-128/64-10YC
Manufacturer:
Lattice
Quantity:
66
Company:
Part Number:
M4A5-128/64-10YC
Manufacturer:
LATTICE
Quantity:
1 831
Company:
Part Number:
M4A5-128/64-10YC
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
M4A5-128/64-10YC
Manufacturer:
LATTICE
Quantity:
20 000
Company:
Part Number:
M4A5-128/64-10YC-12YI
Manufacturer:
LATTICE
Quantity:
4
PAL Block Clock Generation
Each MACH 4 device has four clock pins that can also be used as inputs. These pins drive a
clock generator in each PAL block (Figure 14). The clock generator provides four clock signals
that can be used anywhere in the PAL block. These four PAL block clock signals can consist of
a large number of combinations of the true and complement edges of the global clock signals.
Table 17 lists the possible combinations.
Note:
1. M4(LV)-32/32, M4A(3,5)-32/32, M4(LV)-64/32 and M4A(3,5)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied
to GCLK0, and GCLK3 is tied to GCLK1.
Macrocell-I/O Cell Ratio - Input Switch Matrix
Figure 12. MACH 4 and MACH 4A with 2:1
GCLK2
GCLK3
GCLK1
GCLK0
Figure 14. PAL Block Clock Generator
From Input Cell
17466G-002
MACH 4 Family
Macrocell-I/O Cell Ratio - Input Switch Matrix
Figure 13. MACH 4 and MACH 4A with 1:1
Block CLK2
(GCLK2 or GCLK3)
Block CLK0
(GCLK0 or GCLK1)
Block CLK1
(GCLK1 or GCLK0)
Block CLK3
(GCLK3 or GCLK2)
1
17466G-003
17466G-004
21