ADSP-TS201SABPZ060 Analog Devices Inc, ADSP-TS201SABPZ060 Datasheet - Page 31

• Manufacturer Part Number: ADSP-TS201SABPZ060
• Description: IC, FLOAT-PT DSP, 64BIT, 600MHZ, BGA-576
• Manufacturer: Analog Devices Inc
• Series: TigerSHARCr
• Type: Fixed/Floating Pointr

Specifications of ADSP-TS201SABPZ060

• Frequency: 600MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: HPI
• No. Of I/o's: 4
• Supply Voltage Range: 1.14V To 1.26V, 2.38V To 2.63V
• Interface: Host Interface, Link Port, Multi-Processor
• Clock Rate: 600MHz
• Non-volatile Memory: External
• On-chip Ram: 3MB
• Voltage - I/o: 2.50V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 576-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-TS201S-EZLITE - KIT LITE EVAL FOR ADSP-TS201S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Link Port—Data Out Timing
Table 32
Figure
LVDS link ports.
Table 32. Link Port—Data Out Timing
1
2
3
4
5
6
7
8
9
Parameter Description
Outputs
t
t
t
t
t
t
t
t
t
t
t
Inputs
t
t
Timing is relative to the 0 differential voltage (V
LCR (link port clock ratio) = 1, 1.5, 2, or 4. t
For the cases of t
LCR= 1.
LCR= 1.5.
LCR= 2.
LCR= 4.
The t
TSW is a short-word transmission period. For a 4-bit link, it is 2 × LCR × t
REO
FEO
LCLKOP
LCLKOH
LCLKOL
COJT
LDOS
LDOH
LACKID
BCMPOV
BCMPOH
LACKIS
LACKIH
LDOS
22, and
and t
with
LDOH
Rising Edge
Falling Edge
LxCLKOUT Period
LxCLKOUT High
LxCLKOUT Low
LxCLKOUT Jitter
LxDATO Output Setup
LxDATO Output Hold
Delay from LxACKI rising edge to first transmission
clock edge
LxBCMPO Valid
LxBCMPO Hold
LxACKI low setup to guarantee that the transmitter
stops transmitting
LxACKI high setup to guarantee that the transmitter
continues its transmission without any interruption
(Figure
LxACKI High Hold Time
Figure
LCLKOP
Figure 23
values include LCLKOUT jitter.
= 2.0 ns and t
18,
23)
Figure
provide the data out timing for the
(Figure
(Figure
(Figure
(Figure
(Figure
(Figure
(Figure
LCLKOP
(Figure
19,
(Figure
21)
(Figure
19)
19)
= 12.5 ns, the effect of t
(Figure
Figure
CCLK
(Figure
22)
18)
21)
(Figure
18)
18)
18)
OD
is the core period.
22)
= 0).
20,
20)
20)
23)
Figure
Rev. C | Page 31 of 48 | December 2006
21,
COJT
specification on output period must be considered.
CCLK
. For a 1-bit link, it is 8 × LCR × t
Min
Greater of 2.0 or
0.9 × LCR × t
0.4 × t
0.4 × t
0.25 × LCR × t
0.25 × LCR × t
0.25 × LCR × t
0.25 × LCR × t
0.25 × LCR × t
0.25 × LCR × t
3 × TSW – 0.5
16 × LCR × t
0.51
LCLKOP
LCLKOP
1
1
CCLK
CCLK
1, 9
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
1, 2
1, 2, 3
– 0.10 × t
– 0.15 × t
– 0.30 × t
– 0.10 × t
– 0.15 × t
– 0.30 × t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
ns.
1, 4, 8
1, 5, 6, 8
1, 4, 8
1, 5, 6, 8
1, 7, 8
1, 7, 8
Max
350
350
Smaller of 12.5 or
1.1 × LCR × t
0.6 × t
0.6 × t
±150
±250
16 × LCR × t
2 × LCR × t
4, 5, 6
7
LCLKOP
LCLKOP
ADSP-TS201S
CCLK
1
1
CCLK
CCLK
1, 2
1, 2
1, 2, 3
Unit
ps
ps
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns