ADSP-21161NKCA-100 Analog Devices Inc, ADSP-21161NKCA-100 Datasheet - Page 28

• Manufacturer Part Number: ADSP-21161NKCA-100
• Description: IC, FLOAT-PT DSP, 32BIT, 100MHZ, MBGA225
• Manufacturer: Analog Devices Inc
• Series: SHARCr
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCA-100

• No. Of Bits: 32 Bit
• Frequency: 100MHz
• Supply Voltage: 1.8V
• Embedded Interface Type: HPI, SPI
• No. Of I/o's: 12
• Supply Voltage Range: 1.71V To 1.89V, 3.13V To 3.47V
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ADSP-21161NKCA100

ADSP-21161N
Memory Read — Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN except for ACK pin requirements listed in footnote 4 of
Table 16. Memory Read — Bus Master
1
2
3
4
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
W = (number of wait states specified in WAIT register) × t
HI = t
H = t
Data Delay/Setup: User must meet t
The falling edge of MSx, BMS is referenced.
Data Hold: User must meet t
For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access,
DAD
DRLD
HDA
SDS
HDRH
DAAK
DSAK
SAKC
HAKC
DRHA
DARL
RW
RWR
and dc loads.
ACK must be driven low (deasserted) by t
met for both assertion and deassertion of ACK signal.
CKOP
CKOP
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
Address, Selects Delay to
Data Valid
RD Low to Data Valid
Data Hold from Address,
Selects
Data Setup to RD High
Data Hold from RD High
ACK Delay from Address,
Selects
ACK Delay from RD Low
ACK Setup to CLKIN
ACK Hold After CLKIN
Address Selects Hold
After RD High
Address Selects to RD
Low
RD Pulsewidth
RD High to WR, RD,
DMAGx Low
2
3
2, 4
1, 2
HDA
or t
HDRH
DAD
4
1
, t
in asynchronous access mode. See
DRLD
4
3
DAAK
Min
0
8
1
0.5t
1
0.25t
0.25t
t
0.5t
, or t
CKOP
, t
DSAK
CCLK
CCLK
SDS.
–0.5t
CCLK
CCLK
.
, or t
+3
–1+HI
–1+H
–3
CCLK
SAKC
–1+W
Rev. B | Page 28 of 60 | November 2009
. For the second and subsequent cycles of an asynchronous external memory access, the t
100 MHz
CKOP
Max
t
0.75t
t
t
Example System Hold Time Calculation on Page 55
CKOP
CKOP
CKOP
.
–0.75t
–0.25t
–0.5t
CKOP
–11+W
CCLK
CCLK
CCLK
–12+W
–11+W
Table
the bus master accessing external memory space in asynchro-
nous access mode.
–8.5+W
16. These specifications apply when the ADSP-21161N is
Min
0
8
1
0.5t
1
0.25t
0.25t
t
0.5t
CKOP
CCLK
CCLK
–0.5t
CCLK
CCLK
+3
–1+HI
–1+H
–3
CCLK
–1+W
for the calculation of hold times given capacitive
110 MHz
Max
t
0.75t
t
t
CKOP
CKOP
CKOP
–0.25t
–0.5t
–0.75t
CKOP
–11+W
CCLK
CCLK
CCLK
–12+W
SAKC
–6.75+W ns
–11+W
and t
HAKC
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
must be