ADSP-21062CS-160 Analog Devices Inc, ADSP-21062CS-160 Datasheet - Page 43

• Manufacturer Part Number: ADSP-21062CS-160
• Description: IC, FLOAT-PT DSP, 40BIT, 40MHZ, MQFP-240
• Manufacturer: Analog Devices Inc
• Series: SHARCr
• Type: Floating Pointr

Specifications of ADSP-21062CS-160

• Frequency: 40MHz
• Supply Voltage: 5V
• Embedded Interface Type: HPI, Serial
• No. Of Mips: 40
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +100°C
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 256kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP, 240-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Table 32. Serial Ports—Internal Clock
1
2
Table 33. Serial Ports—Enable and Three-State
1
2
3
4
Table 34. Serial Ports—GATED SCLK with External TFS (Mesh Multiprocessing)
1
Table 35. Serial Ports—External Late Frame Sync
1
2
3
Parameter
Switching Characteristics
t
t
t
t
t
Referenced to drive edge.
For ADSP-21060L/ADSP-21060C, specification is 0.5
Parameter
Switching Characteristics
t
t
t
t
t
t
Referenced to drive edge.
For ADSP-21060L/ADSP-21060C, specification is 3.5 ns min; for ADSP-21062 specification is 4.5 ns min.
For ADSP-21062L, specification is 16 ns max.
For ADSP-21062L, specification is 7.5 ns max.
Parameter
Switching Characteristics
t
t
Applies only to gated serial clock mode used for serial port system I/O in mesh multiprocessing systems.
Parameter
Switching Characteristics
t
t
MCE = 1, TFS enable and TFS valid follow t
For ADSP-21062/ADSP-21062L, specification is 12.75 ns max; for ADSP-21060L/ADSP-21060LC, specification is 12.8 ns max.
For ADSP-21060/ADSP-21060C, specification is 3 ns min.
DFSI
HOFSI
DDTI
HDTI
SCLKIW
DDTEN
DDTTE
DDTIN
DDTTI
DCLK
DPTR
STFSCK
HTFSCK
DDTLFSE
DDTENFS
TFS Delay After TCLK (Internally Generated TFS)
TFS Hold After TCLK (Internally Generated TFS)
Transmit Data Delay After TCLK
Transmit Data Hold After TCLK
TCLK/RCLK Width
Data Enable from External TCLK
Data Disable from External TCLK
Data Enable from Internal TCLK
Data Disable from Internal TCLK
TCLK/RCLK Delay from CLKIN
SPORT Disable After CLKIN
TFS Setup Before CLKIN
TFS Hold After CLKIN
Data Delay from Late External TFS or External RFS with MCE = 1,
MFD = 0
Data Enable from Late FS or MCE = 1, MFD = 0
1, 2
DDTLFSE
2
and t
TSCLK
DDTENFS
– 2 ns min, 0.5t
.
1
1
1
Rev. F | Page 43 of 64 | March 2008
1, 2
1, 4
1, 3
SCLK
+ 2 ns max.
1, 3
1
1
1
Min
–1.5
0
0.5t
Min
4
0
Min
4
Min
3.5
SCLK
–2.5
Max
4.5
7.5
0.5t
Max
10.5
3
22 + 3 DT/8
17
Max
t
Max
12
CK
/2
SCLK
+2.5
ns
Unit
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
Unit
ns
ns
Unit
ns
ns