OX16C950-TQBG OXFORD SEMICONDUCTOR, OX16C950-TQBG Datasheet - Page 25

• Manufacturer Part Number: OX16C950-TQBG
• Description: IC, UART, 1CH, SMD, TQFP48, 950
• Manufacturer: OXFORD SEMICONDUCTOR

Specifications of OX16C950-TQBG

• No. Of Channels: 1
• Data Rate: 15Mbps
• Uart Features: Tx/Rx FIFO INT TRIG
• Supply Voltage Range: 3V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IER[6]: RTS interrupt mask
logic 0 ⇒ Disable the RTS interrupt.
logic 1 ⇒ Enable the RTS interrupt.
This enable is only operative in Enhanced mode
(EFR[4]=1). In non-Enhanced mode, RTS interrupt is
permanently enabled.
IER[7]: CTS interrupt mask
logic 0 ⇒ Disable the CTS interrupt.
logic 1 ⇒ Enable the CTS interrupt.
This enable is only operative in Enhanced mode
(EFR[4]=1). In non-Enhanced mode, CTS interrupt is
permanently enabled.
10.2
The source of the highest priority interrupt pending is
indicated by the contents of the Interrupt Status Register
‘ISR’. There are nine sources of interrupt at six levels of
priority (1 is the highest) as tabulated below:
Note1:
Note2:
Note3:
DS-0031 Sep 05
Level
OXFORD SEMICONDUCTOR LTD.
5
6
2a
2b
1
3
4
-
2
2
Table 14: Interrupt Status Identification Codes
Interrupt Status Register ‘ISR’
ISR[0] indicates whether any interrupts are pending.
Interrupts of priority levels 5 and 6 cannot occur unless
the UART is in Enhanced mode.
ISR[5] is only used in 650 & 950 modes. In 750 mode, it
is ‘0’ when FIFO size is 16 and ‘1’ when FIFO size is
128. In all other modes it is permanently set to ‘0’.
Address-bit detected in 9-bit mode
Special character 1, 2, 3 or 4 or
Special character (XOFF2) or
In-band flow control XOFF or
CTS or RTS change of state
Receiver status error or
Receiver data available
Transmitter THR empty
Modem status change
No interrupt pending
bit 9 set in 9-bit mode
Receiver time-out
Interrupt source
1
ISR[5:0]
see note 3
000001
000110
000100
001100
000010
000000
010000
100000
External—Free Release
10.3
Level 1:
Receiver status error interrupt (ISR[5:0]=’000110’):
Normal (non-9-bit) mode:
This interrupt is active whenever any of LSR[1], LSR[2],
LSR[3] or LSR[4] are set. These flags are cleared following
a read of the LSR. This interrupt is masked with IER[2].
9-bit mode:
This interrupt is active whenever any of LSR[1], LSR[2],
LSR[3] or LSR[4] are set. The receiver error interrupt due
to LSR[1], LSR[3] and LSR[4] is masked with IER[3]. The
‘address-bit’ received interrupt is masked with NMR[1]. The
software driver can differentiate between receiver status
error and received address-bit (9
examining LSR[1] and LSR[7]. In 9-bit mode LSR[7] is only
set when LSR[3] or LSR[4] is set and it is not affected by
LSR[2] (i.e. 9
Level 2a:
Receiver data available interrupt (ISR[5:0]=’000100’):
This interrupt is active whenever the receiver FIFO level is
above the interrupt trigger level.
Level 2b:
Receiver time-out interrupt (ISR[5:0]=’001100’):
A receiver time-out event, which may cause an interrupt,
will occur when all of the following conditions are true:
•
•
•
•
Reading the first data item in RHR clears this interrupt.
Level 3:
Transmitter empty interrupt (ISR[5:0]=’000010’):
This interrupt is set when the transmit FIFO level falls
below the trigger level. It is cleared on an ISR read of a
level 3 interrupt or by writing more data to the THR so that
the trigger level is exceeded. Note that when 16C950 mode
trigger levels are enabled (ACR[5]=1) and the transmitter
trigger level of zero is selected (TTL=0x00), a transmitter
empty interrupt will only be asserted when both the
transmitter FIFO and transmitter shift register are empty
and the SOUT line has returned to idle marking state.
The UART is in a FIFO mode
There is data in the RHR.
There has been no read of the RHR for a period of
time greater than the time-out period.
There has been no new data received and written into
the RHR for a period of time greater than the time-out
period. The time-out period is four times the character
period (including start and stop bits) measured from
the centre of the first stop bit of the last data item
received.
Interrupt Description
th
data bit).
th
OX16C950 rev B
data bit) interrupt by
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