DS90CF364MTD National Semiconductor, DS90CF364MTD Datasheet
DS90CF364MTD
Specifications of DS90CF364MTD
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DS90CF364MTD Summary of contents
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... This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. Block Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation DS90C363/DS90CF364 Features ■ MHz shift clock support ■ ...
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... DS90C363 Order Number DS90C363MTD See NS Package Number MTD48 DS90CF364 Order Number DS90CF364MTD See NS Package Number MTD48 2 1288601 1288624 ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration ...
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Symbol Parameter ICCTG Transmitter Supply Current, 16 Grayscale R ICCTZ Transmitter Supply Current Power Down RECEIVER SUPPLY CURRENT ICCRW Receiver Supply Current, Worst Case ICCRG Receiver Supply Current, 16 Grayscale ICCRZ Receiver Supply Current Power Down Note 1: “Absolute Maximum ...
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Receiver Switching Characteristics Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified Symbol CLHT CMOS/TTL Low-to-High Transition Time CHLT CMOS/TTL High-to-Low Transition Time RSPos0 Receiver Input Strobe Position for Bit 0 RSPos1 Receiver Input Strobe Position for ...
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FIGURE 2. “16 Grayscale” Test Pattern Note 6: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 7: The 16 grayscale test pattern tests device power consumption for a “typical” LCD ...
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FIGURE 4. DS90CF364 (Receiver) CMOS/TTL Output Load and Transition Times FIGURE 5. DS90C363 (Transmitter) Input Clock Transition Time Measurements at Vdiff=0V TCCS measured between earliest and latest LVDS edges → TxCLK Differential Low High Edge FIGURE 6. DS90C363 (Transmitter) Channel-to-Channel ...
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FIGURE 8. DS90CF364 (Receiver) Setup/Hold and High/Low Times FIGURE 9. DS90C363 (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe) FIGURE 10. DS90CF364 (Receiver) Clock In to Clock Out Delay FIGURE 11. DS90C363 (Transmitter) Phase Lock Loop Set Time ...
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FIGURE 12. DS90CF364 (Receiver) Phase Lock Loop Set Time FIGURE 13. Seven Bits of LVDS in One Clock Cycle FIGURE 14. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs 9 1288607 1288609 1288610 www.national.com ...
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FIGURE 17. Transmitter LVDS Output Pulse Position Measurement www.national.com FIGURE 15. Transmitter Power Down Delay FIGURE 16. Receiver Power Down Delay 10 1288621 1288608 1288622 ...
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FIGURE 18. Receiver LVDS Input Strobe Position 11 1288625 www.national.com ...
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C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos—Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note ISI ...
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DS90C363 Pin Descriptions — FPD Link Transmitter Pin Name I TxIN I 21 TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data ...
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Pin Diagrams DS90C363 Truth Table Applications Information The DS90C363 and DS90CF364 are backward compatible with the existing 5V FPD Link transmitter/receiver pair (DS90CF563 and DS90CF564). To upgrade from 3.3V system the following must be addressed: 1. ...
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... Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90C363MTD and DS90CF364MTD Dimensions show in millimeters NS Package Number MTD48 15 www.national.com ...
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