CS43L43-KZ Cirrus Logic Inc, CS43L43-KZ Datasheet
CS43L43-KZ
Specifications of CS43L43-KZ
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CS43L43-KZ Summary of contents
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... CS43L43 operates from a +1 +3.3 V supply and consumes only power with a 1.8 V supply. These features are ideal for portable CD, MP3 and MD players and other portable playback systems that require extremely low power consumption. ORDERING INFORMATION CS43L43-KZ CS43L43-KZZ, Lead Free CDB43L43 DIF1/SDA DIF0/SCL CONTROL PORT INTERFACE DIGITAL VOLUME ...
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... Limiter Release Rate (address 09h) (RRATE) 5.10 Volume and Mixing Control (address 0Ah) ..............................................22 5.11 Mode Control 2 (address 0Bh).................................................................24 6.0 CHARACTERISTICS AND SPECIFICATIONS .................................................25 ANALOG CHARACTERISTICS (CS43L43-KZ)................................................25 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ..27 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ....................30 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www ...
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... Figure 20. Internal Serial Mode Input Timing .................................................................. 31 Figure 21. Internal Serial Clock Generation .................................................................... 31 Figure 22. Control Port Timing - I2C Mode ..................................................................... 32 LIST OF TABLES Table 1. CS43L43 Operational Mode ................................................................................ 6 Table 2. Single-Speed Mode Standard Frequencies ......................................................... 6 Table 3. Double-Speed Mode Standard Frequencies ....................................................... 6 Table 4. Internal SCLK/LRCK Ratio .................................................................................. 7 Table 5. Digital Interface Format - Stand-Alone Mode ...................................................... 7 Table 6 ...
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... Control Port Definitions 6 SCL Serial Control Port Clock (Input) - Serial clock for the control port interface. SDA 15 Serial Control Data I/O (Input/Output) - Input/Output for I 4 LRCK SDATA SCLK/DEM MCLK DIF0/SCL VQ_HP REF_GND CS43L43 RST DIF1/SDA HP_B VA_HP VA GND HP_A FILT data. DS479PP3 ...
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... HP_B CS43L43 5 MCLK 1 LRCK 3 SCLK/DEM 7 VQ_HP 2 SDATA 9 FILT+ 16 RST 6 DIF0/SCL 8 REF_GND 15 DIF1/SDA GND 11 Figure 1. Typical Connection Diagram CS43L43 *Ferrite bead 0.9 to 3.3 V Supply + *1.0 µF 220 µF + µH 47 Ω Ω Headphones 220 µ µ Ω 1.0 µF 1.0 µF 5 ...
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... MCLKDIV bit = 1 in the Mode Control 2 register (address 0Bh Single Speed Mode Double Speed Mode Table 1. CS43L43 Operational Mode , must be synchronously derived from MCLK according to s MCLK (MHz) 384x 512x 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 Table 2 ...
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... DS479PP3 Digital Interface Format Selection Left Justified 24 Right Justified Bits 24, 20 Bits Bits Table 4. Internal SCLK/LRCK Ratio DESCRIPTION 24-bit data Left Justified 24-bit data Right Justified, 24-bit Data Right Justified, 16-bit Data CS43L43 Internal Right Justified SCLK/LRCK 16 Bits Ratio FORMAT FIGURE ...
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... The frequency response of the de-emphasis curve will scale proportionally with changes in sam- ple rate, Fs. De-emphasis is not available in double-speed mode Figure Data + Figure 3. Left Justified up to 24-Bit Data - Figure 4. Right Justified Data Gain dB T1=50 µs 0dB -10dB F1 3.183 kHz 10.61 kHz Figure 5. De-Emphasis Curve CS43L43 µs F2 Frequency equal to s DS479PP3 ...
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... Popguard Transient Control ® The CS43L43 uses Popguard and power-down. This technology, when used with external DC-blocking capacitors in series with the au- dio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters activated inside the DAC when the RST pin is enabled/disabled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors ...
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... GND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance and the output load. For example, with a 220 µF capacitor and a 16 Ω load, the minimum power-down time will be approximately 0.4 seconds. 10 CS43L43 and audio output be- Q DS479PP3 ...
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... otorola M O SFET s show n have been tested to w ork properly, how ever, an equivalent device used F1N H 02E 0uF 47u F1N H 02E 0uF 47u H 1k 100K Figure 6. Optional Headphone Mute Circuit ~ Figure 7. Timing for Headphone Mute CS43L43 H eadphones eadphone O utput at pin of part / ute C ontrol from icroC ontroller 11 ...
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... Figure 1 shows the recommended power arrangements, with VA, VA_HP & VL connected to clean supplies. If the ground planes are split between digital ground and analog ground, the GND pins of the CS43L43 should be connected to the analog ground plane. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwant- ed coupling into the modulators ...
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... C bus followed by the address byte, 00100000. The eighth bit 2 C writes to other registers are desired necessary bus followed by the address byte, 00100001. The eighth bit 2 C read is the first operation performed on the device reads from other registers are desired necessary Figure 8. Control Port Timing CS43L43 ...
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... DVOLA5 DVOLA4 DVOLB6 DVOLB5 DVOLB4 BB2 BB1 BB0 BBCF0 TBCF1 TBCF0 ARATE6 ARATE5 ARATE4 RRATE6 RRATE5 RRATE4 TC0 TC_EN LIM_EN CS43L43 2 1 MAP2 MAP1 MAP0 Reserved Reserved PDN VOLA3 VOLA2 VOLA1 VOLB3 VOLB2 VOLB1 DVOLA3 DVOLA2 DVOLA1 DVOLB3 DVOLB2 DVOLB1 TB3 ...
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... The zero cross function is independently monitored and implemented for each channel. NOTE: Ramped Digital and Analog is not available in Double-Speed mode. DS479PP3 SZC0 POR RESERVED BIT 7 BIT 5-6 CS43L43 2 1 RESERVED PDN CP_EN ...
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... The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation will begin. 5.1.5 CONTROL PORT ENABLE (CP_EN) Default = Disabled 1 - Enabled Function: The Control Port will become active and reset to the default settings when this function is enabled. 16 BIT 4 BIT 1 BIT 0 CS43L43 DS479PP3 ...
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... Table 7. Example Analog Volume Settings NOTE: When the Analog Headphone Attenuation Control registers are set for attenuation levels greater than -10dB, the actual attenuation deviates from the register setting by more than 1dB. DS479PP3 VOLx4 VOLx3 Volume Setting -10 -10 dB -15 -15 dB CS43L43 VOLx2 VOLx1 VOLx0 ...
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... Boost levels are decoded as shown in Table 9. Levels above +12 dB are interpreted as +12 dB. Binary Code Decimal Value 0000 0010 0110 1001 1100 Table 9. Example Bass Boost Settings DVOLx4 DVOLx3 Volume Setting 12 + -60 -60 dB -90 - BB1 BB0 TB3 BIT 4-7 Boost Setting +12 dB CS43L43 DVOLx2 DVOLx1 DVOLx0 TB2 TB1 TB0 DS479PP3 ...
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... TREBLE BOOST CORNER FREQUENCY (TBCF) Default = kHz kHz kHz 11 - Reserved Function: The treble boost corner frequency is user selectable as shown above. NOTE: Treble Boost is not avail- able in Double-Speed Mode. DS479PP3 BIT 0-3 Boost Setting + TBCF0 A BIT 6-5 BIT 4-5 CS43L43 DEM1 DEM0 VCBYP ...
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... Function: When this function is enabled the digital volume control section is bypassed. This disables the digital vol- ume control, muting, bass boost, treble boost, limiting and ATAPI functions. The analog attenuation con- trol will remain functional. 20 BIT 3 BIT 1-2 BIT 0 CS43L43 DS479PP3 ...
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... Use the LIM_EN bit to disable the limiter function (see Section 5.10.3). Binary Code Decimal Value 00000001 00010100 00101000 00111100 01011010 Table 12. Example Limiter Release Rate Settings DS479PP3 ARATE4 ARATE3 LRCK’s per 1 1.6 40 0.8 60 0.53 90 0.356 RRATE4 RRATE3 LRCK’s per 1 512 CS43L43 ARATE2 ARATE1 ARATE0 RRATE2 RRATE1 RRATE0 ...
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... Enabled Function: The CS43L43 will limit the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting is performed by first decreasing the Bass and Treble Boost Levels. If the signal is still clipping, then the digital attenuation is increased. The attack rate is determined by the Limiter Attack Rate register ...
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... ATAPI CHANNEL MIXING AND MUTING (ATAPI) Default = 1001 - HP_A = L, HP_B = R (Stereo) Function: The CS43L43 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Ta- ble 13 and Figure 9 for additional information. NOTE: All mixing functions occur prior to the digital volume control. ...
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... 24-bit data Internal SLCK) DESCRIPTION 24-bit data Internal SLCK 16-bit data Internal SLCK Left Justified 24-bit data, Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 16-bit data Right Justified, 18-bit data Identical to Format 1 CS43L43 DIF2 DIF1 DIF0 Format FIGURE 0 2 ...
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... CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (CS43L43-KZ, KZZ) specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth kHz; test load = 16 Ω (see Figure 10). Typical performance characteristics are derived from measurements taken ° VA_HP = VA = 3.0V and 1.8V. Min/Max performance characteristics are guaranteed over the ...
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... ANALOG CHARACTERISTICS (CS43L43-KZ, KZZ) Parameters Dynamic Performance for All Speed Modes Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Characteristics Full Scale Output Voltage Notes: 1. One-half LSB of triangular PDF dither is added to data kHz) 220 µF + HP_x R L GND Figure 10. Output Test Load ...
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... De-emphasis is only available in Single-Speed Mode. DS479PP3 Min to -0.05 dB corner corner 0 -0.02 (Note 2) 0.5465 50 (Note kHz - kHz - Fs = 44.1 kHz - kHz - to -0.1 dB corner corner 0 0 0.577 55 (Note kHz - kHz - CS43L43 (The Typ Max Unit - 0.4535 Fs - 0.4998 Fs - +0. 9/ ±0.36/ +0.2/-0 +0.05/-0.14 - +0/-0.22 - 0.4426 ...
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... Figure 15. Double-Speed Stopband Rejection 28 Figure 12. Single-Speed Transition Band Figure 14. Single-Speed Passband Ripple 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.6 0.7 0.8 0.9 1.0 0.40 Figure 16. Double-Speed Transition Band CS43L43 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 Frequency (normalized to Fs) 0.58 0.60 DS479PP3 ...
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... Figure 17. Double-Speed Transition Band (Detail) DS479PP3 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 0.51 0.52 0.53 0.54 0.55 0.00 Figure 18. Double-Speed Passband Ripple CS43L43 0.05 0.10 0.15 0.20 0.25 0.30 0.35 Frequency (normalized to Fs) 0.40 0.45 0.50 29 ...
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... Notes: 5. This serial clock is required only in Control Port Mode when the MCLK Divide bit is enabled Figure 19. External Se- 30 Single-Speed Mode Double-Speed Mode (Note 10) t slrs t slrd t sclkl sdlrs rial Mode Input Timing CS43L43 (Inputs: Logic “0” = Symbol Min Max 1.024 51 100 ...
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... Notes Internal SCLK Mode, the LRCK duty cycle must be 50% +/− 1/2 MCLK Period Figure 20. Internal Serial *The SCLK pulses shown are internal to the CS43L43 * The SCLK pulses shown are internal to the CS43L43. DS479PP3 Symbol (Note 6) t sclkw t sclkr t sdlrs Single-Speed Mode ...
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... Stop buf Symbol f scl t irs t buf t hdst t low t high t sust t (Note 7) hdd t sud susp high t hdst sud lo w hdd Figure 22. Control Port Timing - I CS43L43 Min Max - 100 - 1 -------------- - 2 ( )Fs 4.7 - 4.0 - 4.7 - 4 250 - - 300 4 SCL. fc Stop susp hdst t sust Mode Unit ...
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... All Supplies=3.0V VA=1. VA_HP=1.8V I A_HP VL=1.8V I D_L VA=3. VA_HP=3.0V I A_HP VL=3.0V I D_L All Supplies=1.8V All Supplies=3.0V 1 kHz PSRR Q_HP Symbol Min 0 Symbol Min θ JA (Power Applied) T -10 A CS43L43 Min Typ Max Units - 7 1 µ 9.3 - µ 2.0 - µA - 9.3 - µ ...
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... Logic VL (GND = 0 V; all voltages with respect to AGND. Operation Symbol VA_HP V is limited by the Full-Scale Output Voltage V MIN . However, if distortion is not a concern, VA_HP may be FS_HP CS43L43 (GND = 0V; all voltages with respect Min Typ Max Units 1.7 1.8 1.9 V 2.25 2.5 2 ...
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... The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 8.0 REFERENCES 1) CDB43L43 Evaluation Board Datasheet 2 2) “The I C-Bus Specification: Version 2.1” Philips Semiconductors, January 2000. http://www.semiconductors.philips.com DS479PP3 CS43L43 35 ...
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... NOM MAX MIN -- 0.043 -- 0.006 0.05 0.035 0.037 0.85 -- 0.012 0.19 0.197 -- 0.252 -- 0.173 0.177 4.30 0.026 -- 0.024 0.028 0.50 -- 8° JEDEC #: MO-150 CS43L43 E1 A ∝ END VIEW L MILLIMETERS NOM MAX -- -- 1.10 -- 0.15 0.90 0.95 -- 0. 6.40 -- 4.40 4.50 -- 0.65 -- 0.60 0.70 0° ...