CS4396-KSZ Cirrus Logic Inc, CS4396-KSZ Datasheet
CS4396-KSZ
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CS4396-KSZ Summary of contents
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... P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com Description The CS4396 is a complete high performance 24-bit 48/96/192 kHz stereo digital-to-analog conversion sys- tem. The device includes a digital interpolation filter followed by a oversampled multi-bit delta-sigma modula- tor which drives dynamic-element-matching (DEM) selection logic ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 CS4396 DS288PP1 ...
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... Figure 15.Quad-speed Stopband Rejection ............................................................. 24 Figure 16.Quad-speed Transition Band ................................................................... 24 Figure 17.Quad-speed Transition Band ................................................................... 24 Figure 18.Quad-speed Frequency Response .......................................................... 24 Figure 19.De-Emphasis Curve ................................................................................. 24 Figure 20. Format 0, Left Justified ............................................................................ 25 Figure 21. Format 1, I Figure 22. Format 2, Right Justified, 16-Bit Data ..................................................... 25 Figure 23.Format 3, Right Justified, 24-Bit Data ...................................................... 25 DS288PP1 2 C Mode ................................................................. .......................................................................................... 25 CS4396 3 ...
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... TBD A-Weighted TBD unweighted TBD unweighted - A-Weighted - (Note 1) THD - - - - (Note 1) unweighted TBD A-Weighted TBD unweighted TBD unweighted - A-Weighted - (Note 1) THD - - - - CS4396 Typ Max Unit 117 - dB 120 - -100 TBD dB -97 TBD dB -57 TBD 117 - dB 120 - dB 114 - -100 TBD dB -97 ...
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... PSRR - (120 Hz) - Symbol kHz Typ Max Min Typ Max 20 TBD - 20 TBD TBD TBD - TBD TBD TBD TBD - TBD TBD 0 0 Typ Max Min TBD 1.4VREF TBD - 0.5VREF - - 0 100 - - 2.0 TBD 100 - 90 - CS4396 Unit Unit Vpp VDC dB ppm/° ...
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... kHz Fs = 44.1 kHz kHz (Note 4) to -0.1 dB corner corner -0.017 .570 (Note 5) tgd (Note 4) to -0.1 dB corner corner 0.635 (Note 5) tgd CS4396 Min Typ Max - - 0.470 - - 0.492 - +0.015 - - ±0.0001 - - 102 - - - 37/ ± ...
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... VD = 3.0V - 5.25V) A Symbol (AGND = 0 V, all voltages with respect to ground.) Symbol VA VD VREF IND stg (DGND = 0V; all voltages with respect to ground) Symbol Min VD 3.0 VA 4.75 VREF TBD T -10 A CS4396 Min Typ Max Units ± Min Max Unit -0.3 6 ...
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... Fs (Single-speed 256 Fs, (Single-speed 384 Fs, (Single-speed 512 Fs, (Single-speed 768 Fs, (Single-speed mode) (Double-speed mode) (Quad-speed mode) t slrd t slrs t sdlrs t sdh t slrs t slrd t sdlrs Figure 1. Serial Audio Input Timing CS4396 Min Typ Max 100 100 - 200 4.096 - 12.8 6.144 - 19.2 8.192 - 25.6 12 ...
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... Repeated Start t high t t sud t sust hdd 2 Figure Control Port Timing CS4396 = 30 pF) L Min Max Unit - 100 KHz 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - Stop susp hdst ...
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... CCLK CDIN 10 Symbol f sclk t srs (Note 9) t spi t csh t css t scl t sch t dsu (Note 10 (Note 11 (Note 11 css t scl t sch dsu t dh Figure 3. SPI Control Port Timing CS4396 = 30 pF) L Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ 100 ns - 100 all other times. ...
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... Figure 4. Typical Connection Diagram - Hardware Mode (Control Port Mode) DS288PP1 0 VREF M1 FILT+ 4 CS4396 FILT AOUTL- LRCK AOUTL+ SCLK MUTEC SDATA AOUTR- MUTE 1 AOUTR+ RST MCLK CMOUT C/H DGND AGND CS4396 +5V Analog + 1.0 F 0.1 µf +5V 28 Analog 27 0.1 µf 10 µ Analog Conditioning Analog Conditioning 20 25 0.1 µf 10 µ ...
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... The analog outputs will ramp to a normal state when this function transitions from the enabled to disabled state. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The MUTEC will go high immediately on disabling of MUTE. MUTE 0 Enabled 1 Disabled Table MODE MODE CS4396 PDN PDN DS288PP1 ...
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... CAL MUTE Access and SPI. Default Powered Down Function: The analog and digital sections will be placed into a power-down mode when this function is enabled. This bit must be cleared to resume normal operation. PDN 0 Disabled 1 Enabled Table 3. DS288PP1 MODE CS4396 PDN PDN 13 ...
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... SCLK AGND 11 18 LRCK MUTEC 12 17 SDATA C MUTE 14 15 CS4396 Voltage Reference Reference Filter Reference Ground Common ModeS Voltage Differential Output Differential Output Analog Power Analog Ground Differential Output Differential Output Analog Ground Mute Control Control port/Hardware select Soft Mute DS288PP1 ...
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... DS288PP1 MCLK (MHz) 384x 512x 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 MCLK (MHz) 192x 256x 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 MCLK (MHz) 96x 128x 16.9344 22.5792 18.4320 24.5760 CS4396 768x 24.5760 33.8688 36.8640 384x 24.5760 33.8688 36.8640 192x 33.8688 36.8640 15 ...
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... Differential Analog Outpus - AOUTR- , AOUTR+ and AOUTL- , AOUTL+ Pins 19, 20, 23 and 24, Outputs Function: The full scale differential analog output level is specified in the Analog Characteristics specifications table. Analog Power - VA Pin 22, Input Function: Power for the analog and reference circuits. Typically 5VDC. 16 CS4396 DS288PP1 ...
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... C mode, AD0 is a chip address bit used to enable the control port interface in SPI mode. The device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle. DS288PP1 CS4396 17 ...
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... Serial Control Data I/O - SDA/CDOUT Pin 5, Input/Output Function mode, SDA is a data input/output. CDOUT is the control data output for the control port interface in SPI mode Mode Select Pin 14, Input Function: This pin is not used in Control Port Mode and must be terminated to ground. 18 CS4396 DS288PP1 ...
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... APPLICATIONS 5.1 Recommended Power-up Sequence 1. Hold RST low until the power supplies, master, and left/right clocks are stable. 2. Bring RST high. DS288PP1 CS4396 19 ...
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... The control port has 2 modes: SPI and operation is desired, AD0/CS should be tied DGND. If the CS4396 ever detects a high to low transition on AD0/CS after power-up, SPI mode will be selected. 6.1 SPI Mode In SPI mode the CS4396 chip select signal, CCLK is the control port bit clock, CDIN is the input data line from the microcontroller, CDOUT is the data output and the chip address is 0010000 ...
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... Note: If operation is a write, this byte contains the Memory Address Pointer, MAP. DS288PP1 CHIP MAP ADDRESS 0010000 MSB R/W byte 1 MAP = Memory Address Pointer = 0 Figure 5. Control Port Timing, SPI mode ADDR DATA R/W ACK AD0 1-8 Figure 6. Control Port Timing, I CS4396 DATA LSB byte n Note 1 DATA ACK ACK 1-8 Stop 2 C Mode 21 ...
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... Left Justified up to 24-bit data, Format 24-bit data, Format Right Justified 16-bit data, Format Right Justified 24-bit data, Format Left Justified up to 24-bit data, Format 24-bit data, Format Right Justified 16-bit data, Format Right Justified 24-bit data, Format CS4396 FORMAT FIGURE FIGURE DESCRIPTION DESCRIPTION DS288PP1 ...
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... Frequency (normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Frequency (normalized to Fs) 0.45 0.5 0.55 Frequency (normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Frequency (normalized to Fs) CS4396 0.9 0.95 1 0.4 0.45 0.6 0.4 0.45 23 ...
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... Figure 18. Quad-speed Frequency Response µs F2 Frequency 10.61 kHz 0.52 0.54 0.56 0.58 0.6 0.62 0.64 Frequency (normalized to Fs) Figure 16. Quad-speed Transition Band 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (normalized to Fs) CS4396 0.66 0.68 0.7 0.35 0.4 DS288PP1 ...
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... LRCK Left Channel SCLK SDATA clocks Figure 23. Format 3, Right Justified, 24-Bit Data DS288PP1 + LSB MSB - Figure 20. Format 0, Left Justified + LSB MSB - Figure 21. Format Figure 22. Format 2, Right Justified, 16-Bit Data CS4396 Right Channel + LSB Right Channel + LSB 2 S Right Channel Right Channel ...
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... Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB4397 Evaluation Board Datasheet 2 3) “The I C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998. http://www.semiconductors.philips.com 26 CS4396 DS288PP1 ...
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... MAX 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.013 0.697 0.713 0.29G10 0.299 1 0.040 0.060 0.394 0.419 0.016 0.050 0° 8° JEDEC #: MS-013 CS4396 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 17.70 18.10 7.40 7.60 1.02 1.52 10 ...
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