ADC12048CIV National Semiconductor, ADC12048CIV Datasheet - Page 28

• Manufacturer Part Number: ADC12048CIV
• Description: IC, ADC, 13BIT, 216KSPS, LCC-44
• Manufacturer: National Semiconductor

Specifications of ADC12048CIV

• Resolution (bits): 13bit
• Sampling Rate: 216kSPS
• Input Channel Type: Pseudo Differential, Single Ended
• Data Interface: Parallel
• Supply Voltage Range - Analog: 4.5V To 5.5V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Analog Application Information
**
OUTPUT DIGITAL CODE VERSUS ANALOG INPUT
VOLTAGE
The ADC12048’s fully differential 12-bit + sign ADC gener-
ates a two’s complement output that is found by using the
equation shown below:
Round off the result to the nearest integer value between
−4096 and 4095.
INPUT CURRENT
At the start of the acquisition window (t
ing current (due to capacitive switching) flows through the
analog input pins (CH0–CH7, ADCIN+ and ADCIN−, and the
COM). The peak value of this input current will depend on
the amplitude and frequency of the input voltage applied, the
source impedance and the input switch ON resistance. With
the MUXOUT+ connected to the ADCIN+ and the
MUXOUT− connected to the ADCIN− the on resistance is
typically 2800Ω. Bypassing the MUX and using just the
ADCIN+ and ADCIN− inputs the on resistance is typically
2500Ω.
For low impedance voltage sources (
operation), the input charging current will decay to a value
that will not introduce any conversion errors before the end
of the default sample-and-hold (S/H) acquisition time (9
clock cycles). For higher source impedances (
12 MHz operation), the S/H acquisition time should be in-
*
Ceramic
Tantalum
LM4041CI-Adj
LM4040AI-4.1
LM4050
LM4121
LM9140BYZ-4.1
Circuit of Figure 20
FIGURE 20. Low Drift Extremely Stable Reference Circuit
Part Number
<
AcqSYNOUT
1000Ω for 12 MHz
>
1000Ω for
) a charg-
(Continued)
Output Voltage
Tolerance
Adjustable
28
creased to allow the charging current to settle within speci-
fied limits. In asynchronous mode, the acquisition time may
be increased to 15, 47 or 79 clock cycles. If different acqui-
sition times are needed, the synchronous mode can be used
to fully control the acquisition time.
INPUT BYPASS CAPACITANCE
External capacitors (0.01 µF–0.1 µF) can be connected
between the analog input pins (CH0–CH7) and the analog
ground to filter any noise caused by inconductive pickup
associated with long leads.
POWER SUPPLY CONSIDERATIONS
Decoupling and bypassing the power supply on a high reso-
lution ADC is an important design task. Noise spikes on the
V
version errors. The analog comparator used in the ADC will
respond to power supply noise and will make erroneous
conversion decisions. The ADC is especially sensitive to
power supply spikes that occur during the auto-zero or lin-
earity calibration cycles.
The ADC12048 is designed to operate from a single +5V
power supply. The separate supply and ground pins for the
analog and digital portions of the circuit allow separate ex-
ternal bypassing. To minimize power supply noise and ripple,
adequate bypass capacitors should be placed directly be-
tween power supply pins and their associated grounds. Both
supply pins should be connected to the same supply source.
In systems with separate analog and digital supplies, the
ADC should be powered from the analog supply. At least a
A
+ (analog supply) or V
±
±
±
±
±
0.5%
0.1%
0.2%
0.1%
0.5%
Temperature
Coefficient
±
±
±
±
±
100ppm/˚C
100ppm/˚C
±
50ppm/˚C
50ppm/˚C
25ppm/˚C
2ppm/˚C
D
+ (digital supply) can cause con-
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