AD7147ACPZ-1500RL7 Analog Devices Inc, AD7147ACPZ-1500RL7 Datasheet - Page 5

• Manufacturer Part Number: AD7147ACPZ-1500RL7
• Description: IC, CDC, 16BIT, 111SPS, LFCSP-24
• Manufacturer: Analog Devices Inc
• Series: CapTouch™r
• Type: Capacitive Sensor Controllerr

Specifications of AD7147ACPZ-1500RL7

• Resolution (bits): 16bit
• Input Channel Type: Single Ended
• Data Interface: Serial, SPI
• Supply Voltage Range - Digital: 1.65V To 3.6V
• Supply Current: 900µA
• Digital Ic Case Style: CSP
• No. Of Pins: 24
• Voltage Supply Source: Single Supply
• Voltage - Supply: 2.6 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7147EBZ - BOARD EVAL FOR AD7147ACPZEVAL-AD7147-1EBZ - BOARD EVAL FOR AD7147ACPZ-1
• Sampling Rate (per Second): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: AD7147ACPZ-1500RL7TR

SPI TIMING SPECIFICATIONS (AD7147)
T
noted. All input signals are specified with t
Table 4. SPI Timing Specifications
Parameter
f
t
t
t
t
t
t
t
t
SPI Timing Diagram
SCLK
1
2
3
4
5
6
7
8
A
= −40°C to +85°C, sample tested at 25°C to ensure compliance. V
SCLK
SDO
SDI
CS
Limit
5
5
20
20
15
15
20
16
15
t
1
t
4
MSB
t
t
1
2
5
R
= t
2
F
t
= 5 ns (10% to 90% of V
3
3
Figure 2. SPI Detailed Timing Diagram
ns min
ns max
Unit
MHz max
ns min
ns min
ns min
ns min
ns max
ns min
Rev. B | Page 5 of 72
DRIVE
CC
Description
SCLK frequency
CS falling edge to first SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SDI setup time
SDI hold time
SDO access time after SCLK falling edge
CS rising edge to SDO high impedance
SCLK rising edge to CS high
= 1.65 V to 3.6 V, and V
15
) and timed from a voltage level of 1.6 V.
LSB
16
MSB
1
t
6
CC
2
= 2.6 V to 3.6 V, unless otherwise
15
LSB
t
16
8
t
7
AD7147