DP83815DVNG National Semiconductor, DP83815DVNG Datasheet - Page 54

• Manufacturer Part Number: DP83815DVNG
• Description: IC, ENET CTRL 10BASET, 100MBPS, LQFP-144
• Manufacturer: National Semiconductor

Specifications of DP83815DVNG

• Data Rate: 100Mbps
• Ethernet Type: 10BASE-T
• Supply Current: 170mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 144
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Subject to change without notice.
4.0 Register Set
4.2.13.1 CLKRUNN Function
CLKRUNN is a dual-function optional signal. It is used by
the central PCI clock resource to indicate clock status (i.e.
PCI clock running normally or slowed/stopped), and it is
used by PCI devices to request that the central resource
restart the PCI clock or keep it running normally.
In the DP83815, CLKRUNN shares a pin with PMEN (pin
59). This means the chip cannot be simultaneously PCI
Power Management and PCI Mobile Design Guide-
compliant; however, it is unlikely that a system would use
both of these functions simultaneously. The function of the
PMEN/CLKRUNN pin is selected with the CLKRUN_EN bit
of CCSR.
CCSR bits 15 and 8 (PMESTS and PMEEN) are mirrored
from PCI configuration space to allow them to be accessed
by software. The functionality of these bits is the same as
in the PCI configuration register PMCSR.
As an output, CLKRUNN is open-drain like PMEN, i.e. it
can only drive low. CLKRUNN is an input unless one of the
following two conditions occurs:
1. the system drives CLKRUNN high but the DP83815 is
not ready for the PCI clock to be stopped or
2. the PCI clock is stopped or slowed (CLKRUNN is pulled
high by the system) and the DP83815 requires the use of
the PCI bus.
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54
Situation 1 is a “clock continue” event and can occur if the
DP83815 has not completed a pending packet transmit or
receive. Situation 2 is a “clock start” event and can occur if
the DP83815 has been programmed to a WOL state and it
receives a wake packet, or the PCI clock has simply been
stopped and the receiver has data ready to DMA. In either
of these situations, the DP83815 asserts CLKRUNN until it
detects two rising edges of the PCI clock; it then releases
assertion of CLKRUNN. At this point, the central resource
is driving CLKRUNN low, and cannot drive it high again
until at least four rising edges of the PCI clock have
occurred since the initial CLKRUNN assertion by the
DP83815. Also in either situation, the DP83815 must have
detected CLKRUNN de-asserted for two consecutive rising
edges of the PCI clock before it is allowed to assert
CLKRUNN.
NOTES:
* If a clock start or continue event has completed but a PCI
interrupt has not been serviced yet, the CLKRUN logic will
not prevent the system from stopping the PCI clock.
* If PMEEN is not set, the DP83815 cannot assert
CLKRUNN to request a clock start or continue. In this case,
if the system is going to stop the PCI clock, software must
shut down the internal PHY to prevent receive errors.
* If another CLKRUN-enabled device in the system
encounters a clock start or continue event, the cycle of
assertions and de-assertions of CLKRUNN will cause the
DP83815 clock mux to switch the clock to the RX block
back and forth between the PCI clock and the X1 clock
until the event completes.
Rev O
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