CS4221-KS Cirrus Logic Inc, CS4221-KS Datasheet - Page 16

• Manufacturer Part Number: CS4221-KS
• Description: IC, AUDIO CODEC, 24BIT, 50KHZ, SSOP-28
• Manufacturer: Cirrus Logic Inc

Specifications of CS4221-KS

• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 105dB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.5
5.5.1
5.5.2
5.5.3
5.5.4
16
Reserved
7
0
DSP Port Mode (address 05h)
DE-EMPHASIS CONTROL (DEM)
SERIAL INPUT/OUTPUT DATA SCLK POLARITY SELECT (DSCK)
SERIAL DATA OUTPUT FORMAT (DOF)
SERIAL DATA INPUT FORMAT (DIF)
Function:
Function:
Function:
Function:
Default = 00
00 - 44.1 kHz de-emphasis setting
01 - 48 kHz de-emphasis setting
10 - 32 kHz de-emphasis setting
11 - De-emphasis disabled
Selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter re-
sponse at 32, 44.1 or 48 kHz sample rates, see Figure 15.
Default = 0
0 - Data valid on rising edge of SCLK
1 - Data valid on falling edge of SCLK
This function selects the polarity of the SCLK edge used to clock data in and out of the serial audio
port.
Default = 00
00 - I
01 - Left justified
10 - Right justified, 24-bit
11 - Right justified, 20-bit
The required relationship between the left/right clock, serial clock and output serial data is defined by
the Serial Data Output Format, and the options are detailed in Figures 8-11.
Note: If the format selected is Right-Justified, SCLK must be 64 Fs when operating in slave mode.
Default = 00
00 - I
01 - Left justified
10 - Right justified, 24-bit
11- Right justified, 20-bit
The required relationship between the left/right clock, serial clock and input serial data is defined by
the Serial Data Input Format, and the options are detailed in Figures 8-11.
DEM1
2
2
S compatible
S compatible
6
0
DEM0
5
0
DSCK
4
0
DOF1
3
0
DOF0
2
0
CS4220 CS4221
DIF1
1
0
DS284PP3
DIF0
0
0