MMA5206W Freescale Semiconductor, MMA5206W Datasheet - Page 14

• Manufacturer Part Number: MMA5206W
• Description: IC ACCELER 60G X-AXIS 16QFN
• Manufacturer: Freescale Semiconductor

Specifications of MMA5206W

• Sensing Axis: X
• Acceleration: 60 g
• Sensitivity: 0.125 g/LSB
• Package / Case: QFN-16
• Supply Voltage (max): 25 V
• Supply Current: 4 mA to 8 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14
3.1.3.3
Section 4.2.1.2
3.1.3.4
taneous sampling. Reference
3.1.3.5
3.1.3.6
pulse. Reference
3.1.3.7
PSI5 response message. Reference
Note: The PSI5 specification recommends parity for data lengths of 10 bits or less.
MMA52xxWR
The sync pulse pull-down enable bit selects if the sync pulse pull-down is enabled once a sync pulse is detected. Reference
If Daisy Chain Mode is enabled, the Sync Pulse Pull-Down is enabled as listed below:
The latency selection bit selects between one of two data latency methods to accommodate synchronized sampling or simul-
The data size selection bit selects one of two data lengths for the PSI5 response message as shown below.
The PSI5 sync pulse blanking time selection bit selects the timing for ignoring sync pulses after successful reception of a sync
The PSI5 response message error detection selection bit selects either even parity, or a 3-Bit CRC for error detection of the
SYNC_PD
BLANKTIME
0
1
1
1
1
0
1
Sync Pulse Pull-Down Enable Bit (SYNC_PD)
Latency Selection Bit (LATENCY)
Data Size Selection Bit (DATASIZE)
PSI5 Sync Pulse Blanking Time Selection Bit (BLANKTIME)
PSI5 Response Message Error Detection Selection Bit (P_CRC)
for more information regarding the sync pulse pull-down.
Section 4.2.1.1
Daisy Chain Address
Programmed
Latency
0
1
Yes
Yes
Yes
No
x
Section 4.5
for details regarding sync pulse detection and blanking.
Blanking Time determined by end of response transmission for programmed time slot
Section 4.3.3
SYNC_PD
DATASIZE
for more information regarding latency and data synchronization.
Simultaneous Sampling Mode (Latency relative to Sync Pulse)
P_CRC
Synchronous Sampling Mode (Latency relative to Time Slot)
0
1
0
1
Maximum of t
0
1
Command Received
“Run Mode”
for details regarding response message error detection.
Yes
Yes
No
x
x
SYNC_OFF_500
Parity or CRC
Blanking Time Method
Data Latency
Sync Pulse Pull-Down
Parity
CRC
Data Length
or Response Transmission Complete
Disabled
Enabled
Daisy Chain Address = ‘001’
10 Bits
8 Bits
Yes
No
x
x
x
Freescale Semiconductor
Sync Pulse Pull-Down
Disabled
Disabled
Disabled
Enabled
Enabled
Sensors