DC1437B-AB Linear Technology, DC1437B-AB Datasheet - Page 14

• Manufacturer Part Number: DC1437B-AB
• Description: BOARD EVAL LTM9003-AB
• Manufacturer: Linear Technology
• Type: Pre-Distortion Receiver Subsystemr

Specifications of DC1437B-AB

• Design Resources: DC1437 Schematic
• Frequency: 184MHz
• Features: LTM9003 12bit Predistortion Receiver Subsystem, LVDS Output
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Mcu Supported Families: LTM9003
• Development Tool Type: Hardware - Eval/Demo Board
• For Use With/related Products: LTM9003
• Lead Free Status / RoHS Status: Not applicable / Not applicable

LTM9003
operaTion
inputs are both single ended. Low side or high side LO
injection can be used.
The mixer’s RF input consists of an integrated transformer
and a high linearity differential amplifier. The primary
terminals of the transformer are connected to the RF
input (Pin G1) and ground. The secondary side of the
transformer is internally connected to the amplifier’s dif-
ferential inputs.
The mixer’s LO input consists of an integrated transformer
and high speed limiting differential amplifiers. The ampli-
fiers are designed to precisely drive the mixer for the
highest linearity and the lowest noise figure.
Wideband Filter
Most of the IF filtering is done between the mixer and
the IF amplifier. This network is a 2nd order Chebychev
bandpass section, designed for 0.1dB passband ripple.
The 3dB bandwidth is 220MHz, centered at 184MHz, see
Figure 3. Additional lowpass filtering is done just before
the ADC. This filter serves to bandlimit the out of band
noise entering the converter, as well as to isolate the
output of the IF amplifier from the sampling action of the
converter.

–10
–15
–20
–25
–30
–35
–40
–45
–50
–5
0
10
Figure 3. IF Filter Response
60
110
IF FREQUENCY (MHz)
160
210
260
310
360
9003 F03
410
Analog to Digital Converter
As shown in Figure 1, the analog-to-digital converter (ADC)
is a CMOS pipelined multistep converter. The converter
has five pipelined ADC stages; a sampled analog input will
result in a digitized value five cycles later (see the Tim-
ing Diagram section). The encode input is differential for
improved common mode noise immunity. The ADC has
two phases of operation, determined by the state of the
differential ENC
refer to ENC
less than ENC
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and visa versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the Block Diagram. At the instant
that ENC transitions from low to high, the sampled input is
held. While ENC is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H dur-
ing this high phase of ENC. When ENC goes back low, the
first stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When ENC goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third and fourth stages, resulting in a fourth stage residue
that is sent to the fifth stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
+
–
greater than ENC
+
as ENC low.
/ENC
–
input pins. For brevity, the text will
–
as ENC high and ENC
9003f
+